DP83865-EB National Semiconductor, DP83865-EB Datasheet - Page 16

• Manufacturer Part Number: DP83865-EB
• Description: BOARD EVALUATION DP83865
• Manufacturer: National Semiconductor

Specifications of DP83865-EB

• Main Purpose: Interface, Ethernet
• Utilized Ic / Part: DP83865
• Lead Free Status / RoHS Status: Not applicable / Not applicable

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1.0 Pin Description
Pin #
100
101
102
103
104
105
106
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
GTX_CLK/TCK
MDIO
MDC
VSS
IO_VDD
RESERVED
CLK_TO_MAC
CLK_IN
CLK_OUT
MAC_CLK_EN_STRAP
MDIX_EN_STRAP
IO_VDD
VSS
CORE_VDD
VSS
MULTI_EN_STRAP
PHYADDR4_STRAP
AFE_VDD
VSS
PGM_VDD
VSS
1V8_AVDD3
BG_VDD
BG_REF
RX_VDD
VSS
RX_VDD
VSS
Data Sheet Pin Name
(Continued)
Table 1.
16
Reserved Reserved: Leave floating.
Ground Ground: Connect to common ground plane.
Ground Ground: Connect to common ground plane.
Ground Ground: Connect to common ground plane.
Ground Ground: Connect to common ground plane.
Ground Ground: Connect to common ground plane.
Ground Ground: Connect to common ground plane.
Ground Ground: Connect to common ground plane.
Output
Output
Input /
Power
Power
Power
Power
Power
Power
Power
Power
Power
Strap
Strap
Strap
Strap
Type
Input
Input
Input
Input
Input
GMII Transmit Clock: Connect to MAC chip
through a single 50
put has a typical input capacitance of 6 pF
Management Data I/O: This pin requires a 2k
parallel termination resistor (pull-up to VDD).
Management Data Clock: Connect to MAC or
controller using a 50
I/O VDD: (Digital) Connect to 2.5V or 3.3V. The
VDD_SEL pin must be tied accordingly.
Clock to MAC: Connect to the reference clock
input of a GMAC. Use pin
MAC_CLK_EN_STRAP to disable this function.
Clock Input: Connect to external 25MHz refer-
ence clock source. If a crystal is used connect to
first terminal of crystal.
Clock Output: Connect to the second terminal
of a crystal. Leave floating if an external clock
source is used.
Clock to MAC Enable: Use a 2k pull-down re-
sistor to disable. Leave open to enable.
Automatic MDIX Enable: Use a 2k pull-down
resistor to disable. Leave open to enable.
I/O VDD: (Digital) Connect to 2.5V or 3.3V. The
VDD_SEL pin must be tied accordingly.
Core VDD: (Digital) Connect to 1.8V.
Multiple Node Enable: Use a 2k pull-up resis-
tor to enable. Leave open to disable.
PHY Address 4: See section
“5.9 LED/Strapping Option” on page 67 on how
to connect this pin.
AFE VDD: (Analog) Connect to 2.5V.
PGM VDD: Connect to 1.8V through a low pass
filter. See section “5.4 Sensitive Supply Pins” on
page 64 for details.
Analog Supply: Connect to 1.8V through a low
pass filter. See section “5.4 Sensitive Supply
Pins” on page 64 for details.
BG VDD: (Analog) Connect to 2.5V.
BG Reference: See section “5.4 Sensitive Sup-
ply Pins” on page 64 on how to connect this pin.
Receive VDD: (Analog) Connect to 1.8V.
Receive VDD: (Analog) Connect to 1.8V.
Connection / Comment
impedance trace. This in-
impedance trace.