DP83865-EB National Semiconductor, DP83865-EB Datasheet - Page 60

• Manufacturer Part Number: DP83865-EB
• Description: BOARD EVALUATION DP83865
• Manufacturer: National Semiconductor

Specifications of DP83865-EB

• Main Purpose: Interface, Ethernet
• Utilized Ic / Part: DP83865
• Lead Free Status / RoHS Status: Not applicable / Not applicable

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4.0 Functional Description
The CRM is implemented using an advanced digital Phase
Locked Loop (PLL) architecture that replaces sensitive
analog circuitry. Using digital PLL circuitry allows the
DP83865 to be manufactured and specified to tighter toler-
ances.
4.8.9 MLT-3 to NRZ Decoder
The DP83865 decodes the MLT-3 information from the
DSP block to binary NRZI form and finally to NRZ data.
4.8.10 Descrambler
A serial descrambler is used to de-scramble the received
NRZ data. The descrambler has to generate an identical
data scrambling sequence (N) in order to recover the origi-
nal unscrambled data (UD) from the scrambled data (SD)
as represented in the equations:
Synchronization of the descrambler to the original scram-
bling sequence (N) is achieved based on the knowledge
that the incoming scrambled data stream consists of
scrambled IDLE data. After the descrambler has recog-
nized 12 consecutive IDLE code-groups, where an
unscrambled IDLE code-group in 5B NRZ is equal to five
consecutive ones (11111), it will synchronize to the receive
data stream and generate unscrambled data in the form of
unaligned 5B code-groups.
In order to maintain synchronization, the descrambler must
continuously monitor the validity of the unscrambled data
that it generates. To ensure this, a line state monitor and a
hold timer are used to constantly monitor the synchroniza-
tion status. Upon synchronization of the descrambler the
hold timer starts a 722 ms countdown. Upon detection of
sufficient IDLE code-groups (16 idle symbols) within the
722 ms period, the hold timer will reset and begin a new
countdown. This monitoring operation will continue indefi-
nitely given a properly operating network connection with
good signal integrity. If the line state monitor does not rec-
ognize sufficient unscrambled IDLE code-groups within the
722 ms period, the entire descrambler will be forced out of
the current state of synchronization and reset in order to re-
acquire synchronization.
4.8.11 Serial to Parallel Converter
The 100BASE-X receiver includes a Serial to Parallel con-
verter this operation also provides code-group alignment,
and operates on unaligned serial data from the descram-
bler (or, if the descrambler is bypassed, directly from the
MLT-3 to NRZ decoder) and converts it into 5B code-group
data (5 bits). Code-group alignment occurs after the /J/K/
code-group pair is detected. Once the /J/K/ code-group
pair (11000 10001) is detected, subsequent data is aligned
on a fixed boundary.
4.8.12 5B/4B Decoder
The code-group decoder functions as a look up table that
translates incoming 5B code-groups into 4B nibbles. The
code-group decoder first detects the /J/K/ code-group pair
preceded by IDLE code-groups and replaces the /J/K/ with
MAC preamble. Specifically, the /J/K/ 10-bit code-group
pair is replaced by the nibble pair (0101 0101). All subse-
quent 5B code-groups are converted to the corresponding
4B nibbles for the duration of the entire packet. This con-
SD
UD
=
=
UD
SD
N
N
(Continued)
60
version ceases upon the detection of the /T/R/ code-group
pair denoting the End of Stream Delimiter (ESD) or with the
reception of a minimum of two IDLE code-groups.
4.8.13 100BASE-X Link Integrity Monitor
The 100BASE-X Link monitor ensures that a valid and sta-
ble link is established before enabling both the Transmit
and Receive PCS layer. Signal Detect must be valid for at
least 500 ms to allow the link monitor to enter the “Link Up”
state, and enable transmit and receive functions.
4.8.14 Bad SSD Detection
A Bad Start of Stream Delimiter (Bad SSD) is any transition
from consecutive idle code-groups to non-idle code-groups
which is not prefixed by the code-group pair /J/K/.
If this condition is detected, the DP83865 will assert
RX_ER and present RXD[3:0] = 1110 to the MII for the
cycles that correspond to received 5B code-groups until at
least two IDLE code groups are detected.
Once at least two IDLE code groups are detected, RX_ER
and CRS become de-asserted.
4.8.15 Carrier Sense
Carrier Sense (CRS) may be asserted due to receive activ-
ity once valid data is detected via the Smart squelch func-
tion.
For 10/100 Mb/s Half Duplex operation, CRS is asserted
during either packet transmission or reception.
For 10/100 Mb/s Full Duplex operation, CRS is asserted
only due to receive activity.
CRS is deasserted following an end of packet.
4.8.16 Collision Detect and Heartbeat
A collision is detected on the twisted pair cable when the
receive and transmit channels are active simultaneously
while in Half Duplex mode.
Also after each transmission, the 10 Mb/s block will gener-
ate a Heartbeat signal by applying a 1 us pulse on the COL
lines which go into the MAC. This signal is called the Signal
Quality Error (SQE) and it’s function as defined by IEEE
802.3 is to assure the continued functionality of the colli-
sion circuitry.
4.9 Media Independent Interface (MII)
The DP83865 incorporates the Media Independent Inter-
face (MII) as specified in Clause 22 of the IEEE 802.3u
standard. This interface may be used to connect PHY
devices to a MAC in 10/100 Mb/s mode. This section
describes both the serial MII management interface as well
as the nibble wide MII data interface.
The serial management interface of the MII allows for the
configuration and control of multiple PHY devices, gather-
ing of status, error information, and the determination of the
type and capabilities of the attached PHY(s).
The nibble wide MII data interface consists of a receive bus
and a transmit bus each with control signals to facilitate
data transfer between the PHY and the upper layer (MAC).
This section covers the follwing subjects:
— Serial Management Register Access
— Serial Management Access Protocol