DP83865-EB National Semiconductor, DP83865-EB Datasheet - Page 45

• Manufacturer Part Number: DP83865-EB
• Description: BOARD EVALUATION DP83865
• Manufacturer: National Semiconductor

Specifications of DP83865-EB

• Main Purpose: Interface, Ethernet
• Utilized Ic / Part: DP83865
• Lead Free Status / RoHS Status: Not applicable / Not applicable

3.0 Configuration
To enable Auto-MDIX, strapping option pin MDIX_EN
should be pulled up or left floating. Auto-MDIX can be dis-
abled by strapping MDIX_EN pin low. When Auto-MDIX is
disabled, the PMA is forced to either MDI (“straight”) or
MDIX (“crossed”) - according to the setting of the
MAN_MDIX strapping option pin (high for MDIX and low for
MDI).
The two strapping options for the MDI/MDIX configuration
can be overwritten by writing to bits 14 and 15 of register
AUX_CTRL (0x12). Bit 15 disables the Auto-MDIX feature
and bit 14 can change the straight/crossed and MDI/MDIX
setting.
Auto-MDIX is independent of Auto-Negotiation. Auto-MDIX
works in both AN mode and manual forced speed mode.
The Auto-MDIX in forced speed mode is added to
DP83865DVH revision and up.
3.6 Polarity Correction
The GigPHYTER V will automatically detect and correct for
polarity reversal in wiring between the +/- wires for each
pair of the 4 ports.
The current status of the polarity reversals is displayed in
bit 15:12 of register LINK_AN (0x11).
3.7 PHY Address, Strapping Options and LEDs
The PHY address can be set through external strapping
resistors. If all PHY address pins are left floating, the PHY
address is defaulted to 01h by internal pull up/down resis-
tors.
The PHY address of DP83865 port can be configured to
any of the 31 possible PHY addresses (except 00h which
puts the PHY in isolation mode at power-up). However, if
more than one DP83865 is used on a board and if MDIO is
bused in a system, each of the DP83865’s address must
be different.
PHY address strapping pin “0” is shared with the Duplex
LED pin.
Strap option pins can be left floating which will result in the
default for the particular pin to be set. External pull-up or
pull-down resistors (2k
change the pre-set value.
The state of the strapping option pin inputs is latched (into
Strap_reg 0x10) at system power-on or reset. For further
details relating to the latch-in timing requirements of the
strapping option pins, as well as the other hardware config-
uration pins, refer to section “6.2 Reset Timing” on
page 73.
Some strap option pins are shared with LED output pins.
Since the strapping resistor could be a pull-up or a pull-
down, an adaptive mechansim has been implemented to
simplify the required external circuit. In case the LED/strap-
ping pin is strapped high, the LED drive level is active low.
In case the LED/strapping pin is strapped low, the LED
drive level is active high. See section “5.9 LED/Strapping
Option” on page 67 for details of the recommende external
components.
3.8 Reduced LED Mode
The DP83865DVH has a standard five-LED set. In some
applications, it is desirable to use fewer LED’s. The
“reduced LED mode” (RLED) is created to accommodate
the need for combining the LED functions into fewer LED’s
(Continued)
recommended) can be used to
45
and it is implemented on DP83865DVH. Note that the
reduced LED mode is in addition to the existing five-LED
mode.
There are two reduced LED modes, the 3-in-1 mode and
the 4-in-1 mode. The 3-in-1 mode combines 10/100/100
Mbps links status in one LED, the standard LINK10_LED.
In the 3-in-1 mode, the rest of the four LED’s would still
function in the standard mode. This would allow user to use
one LED to indicate three-speed links, and other LED’s to
indicate 1000M link, TX/RX activity, or duplex.
Similar to 3-in-1 mode, the 4-in-1 mode combines an addi-
tional activity into the three-speed link modes. This mode
would further reduce the number of LED’s and still keep the
same number of display types.
To enable the RLED mode, LED Control Register 0x13.5 =
1, and register 0x1A.0 selects 3-in-1 or 4-in-1 mode.
3.9 Modulate LED on Error
The DP83865DVH uses ACT LED to display activity under
normal operation. The ACT LED is steady on when there is
Tx or Rx activity. The ACT can also display gigabit idle
error and CRC event. To differentiate ACT LED from nor-
mal Tx/Rx activity, the rate of the blink is faster when error
occurs. To enable the idle error modulation, LED Control
Register 0x13.3 = 1 and to enable CRC error modulation,
0x13.4 = 1.
3.10 MAC Interface
The DP83865 MAC interface can be configured to one of
the following different modes:
— MII Mode: Supports 10/100 Mbps MACs.
— GMII Mode: Supports 802.3z compliant 1000 Mbps
— RGMII Mode: Supports RGMII version 1.3.
Only one mode is used at a time.
The interface is capable of driving 35 pF under worst condi-
tions. Note that these outputs are not designed to drive
multiple loads, connectors, backplanes, or cables. See
section “5.6 Layout Notes on MAC Interface” on page 66
for design and layout details.
RLED Ena
MACs.
Bit 4
0
0
1
1
0
0
1
1
Table 41. LED Control Reg 0x13
Table 40. Reduced LED Mode
3/4-in-1 Sel
Bit 3
0
1
0
1
0
1
0
1
10/100/1000 link and ACT
ACT/Idle error/CRC error
10/100/1000 link
ACT/CRC error
ACT/Idle error
LINK10_LED
Activity LED
Normal ACT
10M link
10M link
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