DP83865-EB National Semiconductor, DP83865-EB Datasheet - Page 36

• Manufacturer Part Number: DP83865-EB
• Description: BOARD EVALUATION DP83865
• Manufacturer: National Semiconductor

Specifications of DP83865-EB

• Main Purpose: Interface, Ethernet
• Utilized Ic / Part: DP83865
• Lead Free Status / RoHS Status: Not applicable / Not applicable

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2.0 Register Block
14:8
2:0
6:2
1:0
Bit
Bit
15
14
13
12
11
10
15
9
8
7
6
5
4
3
7
mas_sla_err_int_msk
nxt_pg_rcvd_int_msk
rem_flt_cng_int_msk
jabber_cng_int_msk
prl_det_flt_int_msk
mdix_cng_int_msk
dplx_cng_int_msk
Broadcast Enable
spd_cng_int_msk
an_cmpl_int_msk
lnk_cng_int_msk
pol_cng_int_msk
no_hcd_int_msk
Table 21. Expanded Memory Access Control (Exp_mem_ctl) address 0x16 (22’d)
Address Control
no_lnk_int_msk
Global Reset
Bit Name
Reserved
Bit Name
Reserved
Reserved
Table 20. Interrupt Mask Register (INT_MASK) address 0x15 (21’d)
(Continued)
0, RW, SC
[11], RW
Default
Default
0, RW
0, RW
0, RW
0, RW
0, RW
0, RW
0, RW
0, RW
0, RW
0, RW
0, RW
0, RW
0, RW
0, RW
0, RO
0, RO
0, RO
Setting this bit activates the spd_cng_int interrupt. The interrupt
is masked if the bit is cleared.
Setting this bit activates the lnk_cng_int interrupt. The interrupt is
masked if the bit is cleared.
Setting this bit activates the dplx_cng_int interrupt. The interrupt
is masked if the bit is cleared.
Setting this bit activates the mdix_cng_int interrupt. The interrupt
is masked if the bit is cleared.
Setting this bit activates the pol_cng_int interrupt. The interrupt is
masked if the bit is cleared.
Setting this bit activates the prl_det_flt_int interrupt. The interrupt
is masked if the bit is cleared.
Setting this bit activates the mas_sla_err_int interrupt. The inter-
rupt is masked if the bit is cleared.
Setting this bit activates the no_hcd_int interrupt. The interrupt is
masked if the bit is cleared.
Setting this bit activates the no_lnk_int interrupt. The interrupt is
masked if the bit is cleared.
Setting this bit activates the jabber_cng_int interrupt. The inter-
rupt is masked if the bit is cleared.
Setting this bit activates the nxt_pg_rcvd_int interrupt. The inter-
rupt is masked if the bit is cleared.
Setting this bit activates the an_cmpl_int interrupt. The interrupt
is masked if the bit is cleared.
Setting this bit activates the rem_flt_cng_int interrupt. The inter-
rupt is masked if the bit is cleared.
Write as 0, ignore on read.
Global Reset:
This bit resets the entire chip.
Write as 0, ignore on read.
Broadcast Enable:
1 = Respond to broadcast write at MDIO address 0
0 = Respond to MDIO address set in register 0x1F.4:0
Write as 0, ignore on read.
Address Control:
00 = 8-bit expanded memory read/write (auto-incr disabled)
01 = 8-bit expanded memory read/write (auto-incr enabled)
10 = 16-bit expanded memory read/write (auto-incr enabled)
11 = 8-bit expanded memory write-only (auto-incr disabled)
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Description
Description