DP83865-EB National Semiconductor, DP83865-EB Datasheet - Page 40

• Manufacturer Part Number: DP83865-EB
• Description: BOARD EVALUATION DP83865
• Manufacturer: National Semiconductor

Specifications of DP83865-EB

• Main Purpose: Interface, Ethernet
• Utilized Ic / Part: DP83865
• Lead Free Status / RoHS Status: Not applicable / Not applicable

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3.0 Configuration
This section includes information on the various configura-
tion options available with the DP83865. The configuration
options include:
— Accessing expanded memory space
— Manual configuration
— Auto-Negotiation
— Auto-Negotiation register set
— Auto-MDIX configuration
— Automatic polarity correction
— PHY address and LEDs
— Reduced LED mode
— Modulate LED on error
— MII / GMII / RGMII MAC interfaces
— Clock to MAC output
— MII / GMII /RGMII isolate mode
— Loopback mode
— IEEE 802.3ab test modes
— Interrupt
— Power down modes
— Low power mode
— BIST usage
— Cable length indicator
— 10BASE-T HDX loopback disable
— I/O Voltage Selection
— Non-compliant interoperability mode
The DP83865 supports six different Ethernet protocols:
10BASE-T Full Duplex and Half Duplex, 100BASE-TX
Full Duplex and Half Duplex, 1000BASE-T Full Duplex and
Half Duplex. There are three ways to select the speed and
duplex modes, i.e. manual configuration with external
strapping options or through management register write
and Auto-Negotiation.
3.1 Accessing Expanded Memory Space
The 32 IEEE base page registers limits the number of func-
tions and features to be accessed. The advanced propri-
etary features are implemented in the register located in
the expanded memory space. The following are features
and functions require access to expanded memory space:
— Gigabit Speed Fallback
— Gigabit Retry Forced Link
— Cable length indicator
— 10BASE-T HDX loopback
– Speed / Duplex selection
– Forced Master / Slave
– Speed / Duplex selection
– Gigabit speed fallback
– Gigabit retry forced link
– Master / Slave resolution
– Next Page support
– Parallel Detection
– Pause and Asymmetrical Pause resolution
– Restart Auto-Negotiation
– Auto-Negotiation complete time
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There are three registers used for accessing the expanded
memory. The Expanded Memory Access Control resiger
(0x16) sets up the memory access mode, for example, 8-
bit or 16-bit data addess, enable or disable automatic
address increment after each access, and read/write or
write-only opeation. The Expanded Memory Address
pointer register (0x1E) pionts the location of the expanded
memory to be accessed. The Expanded Memory Data
(0x1D) register contains the data read from or write to the
expanded memory.
Note that the order of the writes to these registers is impor-
tant. While register 0x1E points to the internal expanded
address and register 0x1D contains the data to be written
to or read from the expanded memory, the contents of reg-
ister 0x1E automatically increments after each read or
write to data register 0x1D when auto-increment is
selected. Therefore, if data write need to be confirmed,
address register 0X1E should be reloaded with the original
address before reading from data register 0X1D (when
auto-increment is selected).
The expanded memory space data is 8-bit wide. In the 8-bit
read/write mode, the LSB 8 bits of the data register
0x1D.7:0 is mapped to the expanded memory.
The following is an example of step-by-step precedure
enabling the Speed Fallback mode:
— 1) Power down the DP83865 by setting register 0x00.11
— 2) Write to register 0x16 the value 0x0000. This allows
— 3) Write to register 0x1E the value 0x1C0.
— 4) Write to register 0x1D the value 0x0008.
— 5) Take the out of power down mode by resetting register
3.2 Manual Configuration
For manual configuration of the speed and the duplex
modes (also referred to as forced mode) , the Auto-Negoti-
ation function has to be disabled. This can be done in two
ways. Strapping Auto-Negotiation Enable (AN_EN) pin low
disables the Auto-Negotiation. Auto-Negotiation can also
be disabled by writing a “0” to bit 12 of the BMCR 0x00 to
override the strapping option.
It should be noted that manual 1000BASE-T mode is not
supported by IEEE. The DP83865, when in manual
1000BASE-T mode, only communicates with another
National PHY. The manual 1000BASE-T mode is designed
for test purposes only.
3.2.1 Speed/Duplex Selection
In Manual mode, the strapping value of the SPEED[1:0]
pins is used to determine the speed, and the strap value of
the DUPLEX pin is used to determine duplex mode.
For all of the modes above, the DUPLEX strap value “1”
selects Full Duplex (FD), while “0” selects Half Duplex
(HD). The strap values are latched on during power-on
reset and can be overwritten by access to the BMCR regis-
ter 0x00 bits 13,12, 8 and 6.
= 1. This is to ensure that the memory access does not
interfere with the normal operation.
access to expanded memory for 8-bit read/write.
0x00.11.