DP83865-EB National Semiconductor, DP83865-EB Datasheet - Page 59

• Manufacturer Part Number: DP83865-EB
• Description: BOARD EVALUATION DP83865
• Manufacturer: National Semiconductor

Specifications of DP83865-EB

• Main Purpose: Interface, Ethernet
• Utilized Ic / Part: DP83865
• Lead Free Status / RoHS Status: Not applicable / Not applicable

4.0 Functional Description
— In high-speed twisted pair signalling, the frequency con-
— Automatic Attenuation Control (AAC) allows the DSP
4.8.7 Signal Detect
In 100BASE-TX mode, the link is established by detecting
the scrambled idles from the link partner.
In 100BASE-T mode, the signal detect function of the
DP83865 meets the specifications mandated by the ANSI
FDDI TP-PMD Standard as well as the IEEE 802.3
in potentially serious BLW. The digital oscilloscope plot
provided in Figure 9 illustrates the severity of the BLW
event that can theoretically be generated during
100BASE-TX packet transmission. This event consists
of approximately 800 mV of DC offset for a period of 120
ms. Left uncompensated, events such as this can cause
packet loss.
tent of the transmitted signal can vary greatly during nor-
mal operation based primarily on the randomness of the
scrambled data stream and is thus susceptible to fre-
quency dependent attenuation (see Figure 10). This
variation in signal attenuation caused by frequency vari-
ations must be compensated to ensure the integrity of
the transmission. In order to ensure quality transmission
when using MLT-3 encoding, the compensation must be
able to adapt to various cable lengths and cable types
depending on the installed environment. The usage of
long cable length requires significant compensation
which will over-compensate for shorter and less attenu-
ating lengths. Conversely, the usage of short or interme-
diate cable length requiring less compensation will cause
serious under-compensation for longer length cables.
Therefore, the compensation or equalization must be
adaptive to ensure proper level of the received signal in-
dependent of the cable length.
block to fit the resultant output signal to match the limit
characteristic of its internal decision block to ensure error
free sampling.
(Continued)
Figure 9. 100BASE-TX BLW Event
59
100BASE-TX Standard for both voltage thresholds and tim-
ing parameters.
Note that the reception of fast link pulses per IEEE 802.3u
Auto-Negotiation by the 100BASE-X receiver will not cause
the DP83865 to assert signal detect.
4.8.8 Clock Recovery Module
The Clock Recovery Module generates a phase corrected
clocks for the 100BASE-T receiver.
Figure 10. EIA/TIA Attenuation vs. Frequency for 0, 50,
35
30
25
20
15
10
100, 130 & 150 meters of CAT 5 cable
5
0
0
20
40
Frequency (MHz)
60
80
100
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130m
150m
100m
50m
0m
120