DP83865-EB National Semiconductor, DP83865-EB Datasheet - Page 76

• Manufacturer Part Number: DP83865-EB
• Description: BOARD EVALUATION DP83865
• Manufacturer: National Semiconductor

Specifications of DP83865-EB

• Main Purpose: Interface, Ethernet
• Utilized Ic / Part: DP83865
• Lead Free Status / RoHS Status: Not applicable / Not applicable

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6.0 Electrical Specifications
6.5 RGMII Timing
6.5.1 Transmit and Receive Multiplexing and Timing
T
T
T
T
T
T
T
T
T
Note 1: The PC board design requires clocks to be routed such that an additional trace delay of greater than 1.5 ns is added to the associated clock signal.
Note 2: For 10 Mbps and 100 Mbps, Tcyc will scale to 400ns +-40ns and 40ns +-4ns.
Note 3: Duty cycle may be stretched or shrunk during speed changes or while transitioning to a received packet’s clock domain as long as minimum duty
cycle is not violated and stretching occurs for no more that three Tcyc of the lowest speed transitioned between.
Note 4: Guaranteed by design. Not tested.
Parameter
r
skewT
skewT
skewR
setupR
holdR
cyc
Duty_G
Duty_T
/T
f
TX to Clock skew (at receiver, PHY), HP mode
TX to Clock skew (at receiver, PHY), 3COM mode
RX to Clock skew (at transmitter, PHY), HP mode
RX to Clock setup (at transmitter, PHY), 3COM mode
RX to Clock hold (at transmitter, PHY), 3COM mode
Clock Period
Duty Cycle for gigabit
Duty Cycle for 10/100 BASE-T
Rise/Fall Time (20 -80%)
TXEN_ER
RXDV_ER
RX [3:0]
TX [3:0]
TCK
RCK
(Continued)
Description
TXD[3:0]
RXD[3:0] RXD[7:4]
TX_EN
RX_DV
T
skewR
T
setupR
TXD[7:4]
TX_ER
RX_ER
76
RXD[3:0] RXD[7:4]
RX_DV
TXD[3:0]
TX_EN
T
holdR
T
cyc
TX_ER
RX_ER
TXD[7:4]
Note 1
Note 4
Note 4
Note 4
Note 4
Note 2, 4
Note 3
Note 3
Note 4
Notes
T
skewT
T
cyc
-900
-500
Min
1.0
1.4
1.2
7.2
45
40
Typ Max
50
50
8
900
500
2.0
8.8
1.0
55
60
Units
ns
ps
ps
ns
ns
ns
ns
%
%