MC56F8367VPYE Freescale Semiconductor, MC56F8367VPYE Datasheet - Page 4

• Manufacturer Part Number: MC56F8367VPYE
• Description: IC DSP 16BIT 60MHZ 160-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8367VPYE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 76
• Program Memory Size: 544KB (272K x 16)
• Program Memory Type: FLASH
• Ram Size: 18K x 16
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 160-LQFP
• Cpu Family: 56F8xxx
• Device Core Size: 16b
• Frequency (max): 60MHz
• Interface Type: CAN/SCI/SPI
• Total Internal Ram Size: 36KB
• # I/os (max): 76
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 4(4-chx12-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: LQFP
• Data Bus Width: 16 bit
• Processor Series: MC56F83xx
• Core: 56800E
• Numeric And Arithmetic Format: Fixed-Point
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 76
• Data Ram Size: 36 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MC56F8367EVME
• Minimum Operating Temperature: - 40 C
• Package: 160LQFP
• Family Name: 56F8xxx
• Maximum Speed: 60 MHz
• Number Of Timers: 4
• For Use With: MC56F8367EVME - EVAL BOARD FOR MC56F83X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Part 1: Overview . . . . . . . . . . . . . . . . . . . . . . . 5
Part 2: Signal/Connection Descriptions . . . 15
Part 3: On-Chip Clock Synthesis (OCCS) . . 39
Part 4: Memory Operating Modes (MEM) . . 41
Part 5: Interrupt Controller (ITCN) . . . . . . . . 81
Part 6: System Integration Module (SIM) . 111
Part 7: Security Features . . . . . . . . . . . . . . 129
4
1.1. 56F8367/56F8167 Features . . . . . . . . . . . . . 5
1.2. Device Description . . . . . . . . . . . . . . . . . . . . 7
1.3. Award-Winning Development Environment . 9
1.4. Architecture Block Diagram . . . . . . . . . . . . 10
1.5. Product Documentation . . . . . . . . . . . . . . . 14
1.6. Data Sheet Conventions . . . . . . . . . . . . . . . 14
2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2. Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.2. External Clock Operation . . . . . . . . . . . . . . 39
3.3. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.2. Program Map . . . . . . . . . . . . . . . . . . . . . . . 42
4.3. Interrupt Vector Table . . . . . . . . . . . . . . . . . 43
4.4. Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.5. Flash Memory Map . . . . . . . . . . . . . . . . . . . 47
4.6. EOnCE Memory Map . . . . . . . . . . . . . . . . . 49
4.7. Peripheral Memory Mapped Registers . . . . 49
4.8. Factory Programmed Memory . . . . . . . . . . 80
5.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.3. Functional Description . . . . . . . . . . . . . . . . . 81
5.4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 83
5.5. Operating Modes . . . . . . . . . . . . . . . . . . . . . 83
5.6. Register Descriptions . . . . . . . . . . . . . . . . . 84
5.7. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
6.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.3. Operating Modes . . . . . . . . . . . . . . . . . . . . 112
6.4. Operating Mode Register . . . . . . . . . . . . . 112
6.5. Register Descriptions . . . . . . . . . . . . . . . . 113
6.6. Clock Generation Overview . . . . . . . . . . . 127
6.7. Power Down Modes Overview . . . . . . . . . 128
6.8. Stop and Wait Mode Disable Function . . . 128
6.9. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
7.1. Operation with Security Enabled . . . . . . . 129
7.2. Flash Access Blocking Mechanisms . . . . 130
Table of Contents
56F8367 Technical Data, Rev. 9
Part 8: General Purpose Input/Output (GPIO)
Part 9: Joint Test Action Group (JTAG) . 137
Part 10: Specifications . . . . . . . . . . . . . . . 138
Part 11: Packaging . . . . . . . . . . . . . . . . . . 166
Part 12: Design Considerations . . . . . . . . 177
Part 13: Ordering Information . . . . . . . . . 180
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
8.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . 132
8.2. Memory Maps . . . . . . . . . . . . . . . . . . . . . . 132
8.3. Configuration . . . . . . . . . . . . . . . . . . . . . . . 133
9.1. 56F8367 Information. . . . . . . . . . . . . . . . . 137
10.1. General Characteristics. . . . . . . . . . . . . . 138
10.2. DC Electrical Characteristics . . . . . . . . . . 142
10.3. AC Electrical Characteristics . . . . . . . . . . 146
10.4. Flash Memory Characteristics . . . . . . . . . 147
10.5. External Clock Operation Timing . . . . . . . 147
10.6. Phase Locked Loop Timing. . . . . . . . . . . 148
10.7. Crystal Oscillator Timing . . . . . . . . . . . . . 148
10.8. External Memory Interface Timing . . . . . . 149
10.9. Reset, Stop, Wait, Mode Select, and
10.10. Serial Peripheral Interface (SPI) Timing . . . .
10.11. Quad Timer Timing . . . . . . . . . . . . . . . . 157
10.12. Quadrature Decoder Timing . . . . . . . . . . 157
10.13. Serial Communication Interface (SCI)
10.14. Controller Area Network (CAN) Timing . 159
10.15. JTAG Timing . . . . . . . . . . . . . . . . . . . . . 159
10.16. Analog-to-Digital Converter (ADC)
10.17. Equivalent Circuit for ADC Inputs . . . . . . 164
10.18. Power Consumption . . . . . . . . . . . . . . . . 164
11.1. 56F8367 Package and Pin-Out
11.2. 56F8167 Package and Pin-Out
12.1. Thermal Design Considerations . . . . . . . . 177
12.2. Electrical Design Considerations . . . . . . . 178
12.3. Power Distribution and I/O Ring
Interrupt Timing . . . . . . . . . . . . . . 151
Timing . . . . . . . . . . . . . . . . . . . . . 158
Parameters . . . . . . . . . . . . . . . . . 161
Information . . . . . . . . . . . . . . . . . . 166
Information . . . . . . . . . . . . . . . . . . 173
Implementation . . . . . . . . . . . . . . 179
. . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Freescale Semiconductor
Preliminary