MC56F8367VPYE Freescale Semiconductor, MC56F8367VPYE Datasheet - Page 66

IC DSP 16BIT 60MHZ 160-LQFP

MC56F8367VPYE

Manufacturer Part Number
MC56F8367VPYE
Description
IC DSP 16BIT 60MHZ 160-LQFP
Manufacturer
Freescale Semiconductor
Series
56F8xxxr
Datasheets

Specifications of MC56F8367VPYE

Core Processor
56800
Core Size
16-Bit
Speed
60MHz
Connectivity
CAN, EBI/EMI, SCI, SPI
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
76
Program Memory Size
544KB (272K x 16)
Program Memory Type
FLASH
Ram Size
18K x 16
Voltage - Supply (vcc/vdd)
2.25 V ~ 3.6 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 105°C
Package / Case
160-LQFP
Cpu Family
56F8xxx
Device Core Size
16b
Frequency (max)
60MHz
Interface Type
CAN/SCI/SPI
Total Internal Ram Size
36KB
# I/os (max)
76
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
On-chip Adc
4(4-chx12-bit)
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 105C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
160
Package Type
LQFP
Data Bus Width
16 bit
Processor Series
MC56F83xx
Core
56800E
Numeric And Arithmetic Format
Fixed-Point
Device Million Instructions Per Second
60 MIPs
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
76
Data Ram Size
36 KB
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
MC56F8367EVME
Minimum Operating Temperature
- 40 C
Package
160LQFP
Family Name
56F8xxx
Maximum Speed
60 MHz
Number Of Timers
4
For Use With
MC56F8367EVME - EVAL BOARD FOR MC56F83X
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant

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66
PLLCR
PLLDB
PLLSR
SHUTDOWN
OSCTL
COPCTL
COPTO
COPCTR
GPIOA_PUR
GPIOA_DR
GPIOA_DDR
GPIOA_PER
GPIOA_IAR
GPIOA_IENR
GPIOA_IPOLR
GPIOA_IPR
GPIOA_IESR
GPIOA_PPMODE
GPIOA_RAWDATA
Register Acronym
Register Acronym
Register Acronym
Table 4-27 Computer Operating Properly Registers Address Map
Table 4-28 Clock Generation Module Registers Address Map
Table 4-29 GPIOA Registers Address Map
Address Offset
Address Offset
Address Offset
(CLKGEN_BASE = $00 F2D0)
(GPIOA_BASE = $00 F2E0)
$0
$1
$2
$4
$5
(COP_BASE = $00 F2C0)
$0
$1
$2
$A
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
56F8367 Technical Data, Rev. 9
Control Register
Divide-By Register
Status Register
Reserved
Shutdown Register
Oscillator Control Register
Control Register
Time Out Register
Counter Register
Peripheral Enable Register
Interrupt Enable Register
Interrupt Pending Register
Pull-up Enable Register
Data Register
Data Direction Register
Interrupt Assert Register
Interrupt Polarity Register
Interrupt Edge-Sensitive Register
Push-Pull Mode Register
Raw Data Input Register
Register Description
Register Description
Register Description
Reset Value
Freescale Semiconductor
0 x 3FFF
0 x 3FFF
0 x 3FFF
0 x 0000
0 x 0000
0 x 0000
0 x 0000
0 x 0000
0 x 0000
0 x 0000
Preliminary

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