EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 156

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

5
MIRClkDiv
5-30
System Controller
EP93xx User’s Guide
MENA
31
15
Address:
Default:
Definition:
Bit Descriptions:
ESEL
30
14
PSEL
29
13
28
12
0x8093_0088 - Read/Write, Software locked
0x0000_0000
Configures MIR clock for the MIR IrDA. Selects input to MIR clock dividers
from either PLL1 or PLL2, and defines a programmable divide value.
RSVD:
MENA:
ESEL:
PSEL:
PDIV:
MDIV:
RSVD
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Reserved. Unknown During Read.
Enable MIR_CLK divider.
External clock source select.
0 - Use the external XTALI clock input as the clock source.
1 - Use one of the internal PLLs selected by PSEL as the
clock source.
PLL source select.
1 - Select PLL2 as the clock source.
0 - Select PLL1 as the clock source.
Pre-divider value. Generates divide by 2, 2.5, or 3 from the
clock source.
00 - Disable clock
01 - Divide-by-2
10 - Divide-by-2.5
11 - Divide-by-3
MIR_CLK divider value. Forms a divide-by-N of the pre-
divide clock output. MIR_CLK is the source clock divided
by PDIV divided by N.
PDIV
24
8
RSVD
RSVD
23
7
22
6
21
5
20
4
MDIV
19
3
18
2
17
1
DS785UM1
16
0