EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 465

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

HcFmRemaining
DS785UM1
FRT
31
15
Address:
Default:
Definition:
Bit Descriptions:
RSVD
30
14
29
13
28
12
RSVD:
FI:
FSMPS:
FIT:
0x8002_0038
0x0000_0000
Contains the time remaining in the current frame.
RSVD:
FR:
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Reserved. Unknown During Read.
FrameInterval. This specifies the interval between two
consecutive SOFs in bit times. The nominal value is set to
be 11,999. HCD should store the current value of this field
before resetting HC. By setting the HostControllerReset
field of HcCommandStatus as this will cause the HC to
reset this field to its nominal value. HCD may choose to
restore the stored value upon the completion of the Reset
sequence.
FSLargestDataPacket. This field specifies a value which is
loaded into the Largest Data Packet Counter at the
beginning of each frame. The counter value represents the
largest amount of data in bits which can be sent or
received by the HC in a single transaction at any given
time without causing scheduling overrun. The field value is
calculated by the HCD.
FrameIntervalToggle. HCD toggles this bit whenever it
loads a new value to FrameInterval.
Reserved. Unknown During Read.
FrameRemaining. This counter is decremented at each bit
time. When it reaches zero, it is reset by loading the
FrameInterval value specified in HcFmInterval at the next
bit time boundary. When entering the USBOPERATIONAL
state, HC re-loads the content with the FrameInterval of
HcFmInterval and uses the updated value from the next
SOF.
24
8
RSVD
23
7
FR
22
6
21
5
Universal Serial Bus Host Controller
20
4
19
3
EP93xx User’s Guide
18
2
17
1
11-25
16
0
11