EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 554

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

14
UART1HDLCSts
14-32
UART1 With HDLC and Modem Control Signals
EP93xx User’s Guide
LNKIDL
31
15
Definition:
Bit Descriptions:
CRE
30
14
ROR
29
13
TBY
28
12
HDLC Receive Information Buffer Register. This register is loaded when the
last data byte in a received frame is read from the receive FIFO. The CPU has
until the end of the next frame to read this register, or the RIL bit in the HDLC
Status Register is set.
RSVD:
BPLLE:
BC:
BFRE:
BROR:
BCRE:
BRAB:
RIF
27
11
RSVD
26
10
Copyright 2007 Cirrus Logic
RAB
25
9
Reserved. Unknown During Read.
Buffered Digital PLL Error.
1 - Receiver aborted last frame because DPLL lost the
carrier.
0 - Receiver did not abort because DPLL lost the carrier.
This bit is only valid when receiving Manchester-encoded
synchronous HDLC.
Received frame Byte Count.
The total number of valid bytes read from the RX FIFO
during the last HDLC frame.
Buffered Framing Error.
0 - No framing errors were encountered in the last frame.
1 - A framing error occurred during the last frame, causing
the remainder of the frame to be discarded.
Buffered Receiver Over Run.
0 - The RX buffer did not overrun during the last frame.
1 - The receive FIFO did overrun during the last frame.
The remainder of the frame was discarded.
Buffered CRC Error.
0 - No CRC check errors occurred in the last frame.
1 - The CRC calculated on the incoming data did not
match the CRC value contained in the last frame.
Buffered Receiver Abort.
0 - No abort occurred in the last frame.
1 - The last frame was aborted.
RSVD
RTO
24
8
EOF
23
7
RFL
22
6
RIL
21
5
RFC
20
4
RFS
19
3
TAB
18
2
PLLE
TFC
17
1
DS785UM1
PLLCC
TFS
16
0