EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 768

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

26
Register Descriptions
KeyScanInit
26-6
Keypad Interface
EP93xx User’s Guide
26.2.4 Low Power Mode
26.2.5 Three-key Reset
26.3 Registers
DIS3KY
31
15
The key scanning block also supports a low power wake-up mode. In this mode, a key press
generates a wake up interrupt. The key scan interrupt should be masked. Because the wake
up interrupt is asynchronous, and depends on external keypad lines which may have a large
capacitance value, glitches may occur on the interrupt when transitioning to low power mode.
After transitioning, all clocks to the key scanning circuitry can be shut down. In the low power
mode, all of the column line drivers should be in input mode in a high state due to the pad pull
up resistors. The column inputs are ANDed together to detect any key presses. This signal
directly toggles the interrupt output. The detect condition is not de-bounced.
The key scanning circuitry provides a three-key reset output by detecting keys (columns) 2,
4, and 7 activated in row 0. The three-key reset detect is used by the watchdog circuit to
generate a three-key initiated reset to the system.
The output RESET_KEYS_DETECTED goes to the Watchdog block to indicate that a three-
key reset is being requested.
DIAG
Note: Key scan controller registers are intended to be word accessed only. Since the least
30
14
significant bytes of the address bus are not decoded, byte and half word accesses are not
allowed and may have unpredictable results.
BACK
29
13
0x808F_0000
0x808F_0004
0x808F_0008
Address
28
12
T2
RSVD
27
11
KeyDiagnostic
NA
KeyRegister
KeyScanInit
Name
26
10
Table 26-1. Keypad Interface Register Memory Map
Copyright 2007 Cirrus Logic
25
9
SW locked
24
8
No
No
No
23
7
Read/Write
Read/Write
Read Only
Type
22
6
24 bits
16 bits
21
5
6 bits
Size
PRSCL
20
4
Key Scan Initialization Register
Key Scan Diagnostic Register
DBNC
Key Value Capture Register
19
3
Description
18
2
17
1
DS785UM1
16
0