EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 50

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

2
2-12
ARM920T Core and Advanced High-Speed Bus (AHB)
EP93xx User’s Guide
2.3.2 AHB-to-APB Bridge
2.3.2.1 Function and Operation of the AHB-to-APB Bridge
The AHB-to-APB Bridge is an AHB slave that provides an interface between the high-speed
AHB and the low-power APB. Read and write transfers on the AHB are converted into
equivalent transfers on the APB. As the APB is not pipelined. Wait states are added during
transfers to and from the APB when the AHB is required to wait for the APB.
The main sections of this bridge are:
The AHB-to-APB Bridge responds to access requests from the currently granted AHB
master. The AHB accesses are then converted into APB accesses.
If an undefined location is accessed, operation of the system continues as normal, but no
peripherals are selected. The APB bridge acts as the only master on the APB.
The APB memory map is shown in
• AHB slave bus interface
• APB transfer state machine, which is independent of the device memory map
• APB output signal generation.
0x808D_0000 - 0x808D_FFFF
0x808C_0000 - 0x808C_FFFF
0x808F_0000 - 0x808F_FFFF
0x808E_0000 - 0x808E_FFFF
0x808B_0000 - 0x808B_FFFF
0x808A_0000 - 0x808A_FFFF
0x8095_0000 - 0x9000_FFFF
0x8094_0000 - 0x8094_FFFF
0x8093_0000 - 0x8093_FFFF
0x8092_0000 - 0x8092_FFFF
0x8091_0000 - 0x8091_FFFF
0x8090_0000 - 0x8090_FFFF
0x8089_0000 - 0x8089_FFFF
0x8088_0000 - 0x8088_FFFF
0x8087_0000 - 0x8087_FFFF
0x8086_0000 - 0x8086_FFFF
0x8085_0000 - 0x8085_FFFF
0x8084_0000 - 0x8084_FFFF
0x8083_0000 - 0x8083_FFFF
0x8082_0000 - 0x8082_FFFF
0x8081_0000 - 0x8081_FFFF
0x8080_0000 - 0x8080_FFFF
0x8010_0000 - 0x807F_FFFF
Address Range
Table 2-3. APB Peripheral Address Range
Copyright 2007 Cirrus Logic
Table
Register
Width
16
32
32
16
32
16
32
32
32
16
32
16
32
32
32
8
-
-
-
-
-
-
-
2-3.
Peripheral
Type
APB
APB
APB
APB
APB
APB
APB
APB
APB
APB
APB
APB
APB
APB
APB
APB
-
-
-
-
-
-
-
Reserved
Watchdog Timer
Syscon
Real time clock
Pulse Width Modulation
Touchscreen
Key Matrix
UART3
UART2
UART1
IrDA
SPI
Reserved
AAC
Reserved
Reserved
Reserved
GPIO
Security
I2S
Timers
Reserved
Reserved
Peripheral
DS785UM1