EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 306

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

9
9-4
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
In the receiver, the MAC detects the preamble and locks onto the embedded clock. The MAC
performs destination address filtering (individual, group, broadcast, promiscuous) on the DA.
The MAC engine computes the correct FCS, and reports if the received FCS is “good” or
“bad”. The data after the SFD and before the FCS is supplied to the host as the received
data. The received FCS may also be passed to the host by setting RXCtl.BCRC.
D ire c tio n o f T ra n s m is sio n
alternating 1s / 0s
up to 7 bytes
p re am b le
S F D = S ta rt o f F ra m e D e lim ite r
D A = D e s tin a tio n A d d re s s
S A = S o u rc e A d d re ss
L L C = L o gic a l L in k C o n tro l
F C S = F ra m e C h e c k S e q u e n c e (s o m etim e s
c a lle d C y c lic R e d u nd a n c y C h e c k , o r C R C )
Figure 9-2. Ethernet Frame / Packet Format (Type II only)
E th e rn e t F ra m e /P a c k e t F o rm a t (T y p e II, o n ly )
S F D
1 byte
6 bytes
D A
Copyright 2007 Cirrus Logic
Packet
6 bytes
SA
optional field
m a x 1 5 1 8 b yte s
fra m e le n g th
m in 6 4 b y te s
2 bytes
F ra m e
T he o ptio n a l fie ld , w h ic h is tw o by te s
lon g, is eith er a T Y P E field fo r E th e rne t
a pp lic atio n s ,o r is a L E N G T H fie ld for
IE E E 80 2.3 a pplic atio n s .
T he P ad fie ld w ill b e u s e d o nly to ge t
th e fra m e to th e m inim u m s ize .
S e e p a ra g ra p h 6 .3 .3.
W he n th e C S 8 93 1 ad d s p ad b y tes ,
th e p ad is the la st b yte of th e
L LC da ta fie ld re p ea te d M tim es .
LL C da ta
N bytes
M bytes
Pad
4 bytes
F C S
DS785UM1