EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 414

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

10
10-20
DMA Controller
EP93xx User’s Guide
10.2.1 DMA Controller Memory Map
10.2 Registers
During normal operation, using the “fair” rotating priority scheme shown in
channel to be serviced becomes the lowest priority channel with the others rotating
accordingly. In addition, any device requesting service is guaranteed to be recognized after
no more than eleven higher priority services has occurred. This prevents any one channel
from monopolizing the system. When the bus is idle, the scheme reverts to a fixed priority
whereby the highest priority request gets in first (as shown in
resumes to normal operation.
In the case where the two M2M channels are requesting a service, the [PW] size of the read
or write transfers for the first channel are completed before the read transfer for the second
channel begins. See subsections under
handshaking protocols for hardware and software-triggered M2M channel transfers.
Table 10-3
channels (5 Tx and 5 Rx), plus the 2 M2M (memory-to-memory) channels.
Before programming a channel, the clock for that channel must be turned on by setting the
appropriate bit in the PwrCnt register of the Clock and State Controller block.
0x8000_0080 -> 0x8000_00BC
0x8000_00C0 -> 0x8000_00FC
0x8000_0180 -> 0x8000_01BC
0x8000_01C0 -> 0x8000_01FC
0x8000_0280 -> 0x8000_02BC
0x8000_02C0 -> 0x8000_02FC
0x8000_0000 -> 0x8000_003C
0x8000_0040 -> 0x8000_007C
0x8000_0100 -> 0x8000_013C
0x8000_0140 -> 0x8000_017C
0x8000_0200 -> 0x8000_023C
0x8000_0240 -> 0x8000_027C
0x8000_0300 -> 0x8000_033C
ARM920T Address
Lowest
defines the DMA Controller mapping for each of 10 M2P (memory-to-peripheral)
Table 10-2. M2P DMA Bus Arbitration (Continued)
Table 10-3. DMA Memory Map
Copyright 2007 Cirrus Logic
Internal Arbitration Priority
M2P Channel 1 Registers (Rx)
M2P Channel 3 Registers (Rx)
M2P Channel 5 Registers (Rx)
M2P Channel 7 Registers (Rx)
M2P Channel 9 Registers (Rx)
CHARB = 0
M2P Channel 0 Registers (Tx)
M2P Channel 2 Registers (Tx)
M2P Channel 4 Registers (Tx)
M2P Channel 6 Registers (Tx)
M2M Ch 0
M2M Ch 1
M2P Ch 7
M2P Ch 8
M2P Ch 9
M2M Channel 0 Registers
M2M Channel 1 Registers
Description
Not Used
Not Used
Section 10.1.5
for detailed information about
Channel Base Address
Table
CHARB = 1
M2P Ch 5
M2P Ch 6
M2P Ch 7
M2P Ch 8
M2P Ch 9
0x8000_00C0
0x8000_02C0
0x8000_0000
0x8000_0040
0x8000_0080
0x8000_0100
0x8000_0140
0x8000_0200
0x8000_0240
0x8000_0280
0x8000_0300
10-2) when the bus
Table
10-2, the last
DS785UM1