EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 263

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

SigClrStr
DS785UM1
31
15
Address: 0x8003_0210
Default: 0x0000_0000
Definition: Signature Clear and Store Location register
Bit Descriptions:
30
14
RSVD
RSVD
29
13
28
12
RSVD:
VCLR:
HCLR:
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
The STRT value is the value of the horizontal down
counter at which the HSIGEN signal becomes active
(starts). This indicates the start of the signature calculation
for a horizontal line. HSIGEN is an internal block signal.
The SIG_ENABLE control to the video signature analyzer
is enabled by the logical AND of VSIGEN and HSIGEN.
Reserved. Unknown during read.
Vertical Clear - Read/Write
The VCLR value is the value of the Vertical down counter
at which the VSIGCLR signal is active. This indicates the
line for clearing the LFSR and storing the result value for
the Vertical frame. VSIGCLR is an internal block signal.
The SIG_CLR control to the video signature analyzer is
generated by the logical AND of VSIGCLR and HSIGCLR.
The SigClrStr control signal is also routed to an edge
trigger capable interrupt on the interrupt controller for use
as a programmable secondary raster engine interrupt
output.
Horizontal Clear - Read/Write
The HCLR value is the value of the Vertical down counter
at which the HSIGCLR signal is active. This indicates the
specific horizontal pixel clock for clearing the LFSR and
storing the result value within a horizontal line. HSIGCLR
is an internal block signal. The SIG_CLR control to the
video signature analyzer is generated by the logical AND
of VSIGCLR and HSIGCLR. The SigClrStr control signal is
also routed to an edge trigger capable interrupt on the
interrupt controller for use as a programmable secondary
raster engine interrupt output.
Raster Engine With Analog/LCD Integrated Timing and Interface
24
8
23
7
22
6
HCLR
VCLR
21
5
20
4
19
3
EP93xx User’s Guide
18
2
17
1
16
7-81
0
7