EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 719

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

DS785UM1
23.5.8 Motorola SPI Format with SPO=0, SPH=1
SFRMOUT /
SFRMIN
SCLKOUT /
SCLKIN
The transfer signal sequence for Motorola SPI format with SPO=0, SPH=1 is shown in
Figure
In this configuration, during idle periods:
If the SSP is enabled and there is valid data within the transmit FIFO, the start of
transmission is signified by the SFRMOUT master signal being driven LOW. The master
SSPTXD output pad is enabled. After a further one half SCLKOUT period, both master and
slave valid data is enabled onto their respective transmission lines. At the same time, the
SCLKOUT is enabled with a rising edge transition.
Data is then captured on the falling edges and propagated on the rising edges of the
SCLKOUT signal.
In the case of a single word transfer, after all bits have been transferred, the SFRMOUT line
is returned to its idle HIGH state one SCLKOUT period after the last bit has been captured.
For continuous back-to-back transfers, the SFRMOUT pin is held LOW between successive
data words and termination is the same as that of the single word transfer.
SSRXD
SSTXD
SSPOE
• the SCLKOUT signal is forced LOW
• SFRMOUT is forced HIGH
• the transmit data line SSPTXD is arbitrarily forced LOW
• when the SSP is configured as a master, the SSPCTLOE line is driven LOW, enabling
• when the SSP is configured as a slave, the SSPCTLOE line is driven HIGH, disabling
the SCLKOUT pad (active LOW enable)
the SCLKOUT pad (active LOW enable).
23-5, which covers both single and continuous transfers.
Q
Figure 23-5. Motorola SPI Frame Format with SPO=0 and SPH=1
M SB
MS B
Copyright 2007 Cirrus Logic
4 t o 16 bi t s
Synchronous Serial Port
EP93xx User’s Guide
LS B
LS B
Q
23-7
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