R5F363AENFA#U0 Renesas Electronics America, R5F363AENFA#U0 Datasheet - Page 644

• Manufacturer Part Number: R5F363AENFA#U0
• Description: MCU 4KB FLASH 256/16K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: M16C/60/63r

Specifications of R5F363AENFA#U0

• Core Processor: M16C/60
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, SIO, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/63 Group
REJ09B0510-0100 Rev.1.00 Sep 15, 2009
Page 606 of 836
26.2.3
Figure 26.2
CREGFLG bit
CREGCLR bit
CTXDEN (Transmit enable bit) (b0)
CRXDEN (Receive enable bit) (b1)
When changing the values of these bits, transmission/reception is enabled or disabled after one or
more cycles of the clock source elapses.
CREGCLR (Receive edge detect flag clear bit) (b2)
The CREGFLG bit in the CECC4 register becomes 0 by setting the CREGCLR bit to 1 when CEC input
is Hi-Z. When CEC input is low, the CREGFLG bit remains unchanged even if the CREGCLR bit is set
to 1.
The CREGCLR bit retains the value written to it.
In order set the CREGFLG bit to 0 again by setting the CREGCLR bit to 1, first set the CREGCLR bit to
0, then set it to 1.
Figure 26.2 shows the Operation of Bits CREGFLG and CREGCLR.
CREGCLR: Bit in the CECC3 register
CREGFLG: Bit in the CECC4 register
CEC Function Control Register 3
b7 b6 b5 b4 b3 b2 b1 b0
CEC Function Control Register 3 (CECC3)
CEC
Operation of Bits CREGFLG and CREGCLR
Becomes 1 when CEC
is low.
CREGCLR
Bit Symbol
CRXDEN
CTXDEN
Symbol
CECC3
CEOMI
(b7-b4)
—
Transmit enable bit
Receive enable bit
Receive edge detect flag
clear bit
EOM disable bit
No register bits. If necessary, set to 0. Read as undefined value
The CREGFLG bit
becomes 0 by setting
the CREGCLR bit to 0
when CEC is high.
Bit Name
Address
0352h
26. Consumer Electronics Control (CEC) Function
0: Disabled
1: Enabled
0: Disabled
1: Enabled
The CREGFLG bit in the CECC4
register becomes 0 by setting 1 to
this bit
0: EOM enabled
1: EOM disabled (EOM ignored)
Becomes 1 when CEC is low.
(The CREGFLG bit remains
unchanged even if the
CREGCLR bit is set to 1.)
Function
XXXX 0000b
After Reset
RW
RW
RW
RW
RW
—