R5F363AENFA#U0 Renesas Electronics America, R5F363AENFA#U0 Datasheet - Page 876

• Manufacturer Part Number: R5F363AENFA#U0
• Description: MCU 4KB FLASH 256/16K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: M16C/60/63r

Specifications of R5F363AENFA#U0

• Core Processor: M16C/60
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, SIO, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev.
Revision History
Date
181, 182 Figure 13.6 “I/O Ports (6/9)” and Figure 13.7 “I/O Ports (7/9)” notes added
Page
120
122
124
126
129
130
141
143
157
194
217
219
230
238
238
252
264
269
286
290
302
312
322
323
337
343
358
117
117
9.3.1.5 “Low-Speed Mode” fC division modified
9.3.1.6 “Low Power Mode” fC division modified
9.3.2 “Clock Mode Transition Procedure” a and d to h → a and d to i
9.3.3.1 “Peripheral Function Clock Stop Function” fOCO40M added
Table 9.8 “Resets and Interrupts to Exit Wait Mode and Conditions for Use”
partially modified
Table 9.9 “Pin Status in Stop Mode” partially modified
9.4.2.1 “Slow Read Mode” 5 MHz → f(SLOW_R)
Figure 9.4 “Setting and Canceling Low Current Consumption Read Mode”
partially modified
Table 11.1 “Bus Specifications” partially modified
11.2.1 “Chip Select Control Register (CSR)” partially modified
Table 11.11 “Bits and Bus Cycles Related to Software Wait States
(External Area)” note added
13.4.2 “Priority Level of Peripheral Function I/O” partially deleted
Table 14.7 “Relocatable Vector Tables (2/2)” note partially modified
Figure 14.3 “Time Required for Executing Interrupt Sequence” note
partially modified
Figure 14.12 “Procedure for Changing the Interrupt Generate Factor”
partially modified
15.3 “Optional Function Select Area” partially added
15.3.1 “Optional Function Select Address 1 (OFS1)” partially modified
Table 16.7 “Timing at Which the DMAS Bit Changes State” partially
modified
Table 17.3 “I/O Ports” partially modified
17.2.5 “Timer A Count Source Select Register 2 (TACS2) (i = 0 to 2)”
partially modified
Table 17.8 “Event Counter Mode Specifications (When Not Processing
Two-Phase Pulse Signal)” partially modified
Table 17.10 “Event Counter Mode Specifications (When Processing Two-
Phase Pulse Signal with Timers A2, A3, and A4)” partially modified
Figure 17.11 “Operation Example in 16-Bit Pulse Width Modulation Mode”
partially modified
17.5.6.2 “Stop While Counting” partially modified
18.2.7 “Timer B Count Source Select Register i (TBCSi) (i = 0 to 3)”
partially modified
18.2.8 “Timer AB Division Control Register 0 (TCKDIVC0)” partially
modified
Figure 18.7 “Operation Example in Pulse Width Measurement Mode”
partially modified
Figure 19.1 “Three-Phase Motor Control Timer Function Block Diagram 1”
partially modified
19.3.1.6 “Three-Phase PWM Waveform Output Pins” partially modified
M16C/63 Group Hardware Manual
C - 2
Description
Summary