R5F363AENFA#U0 Renesas Electronics America, R5F363AENFA#U0 Datasheet - Page 681

MCU 4KB FLASH 256/16K 100-QFP

R5F363AENFA#U0

Manufacturer Part Number
R5F363AENFA#U0
Description
MCU 4KB FLASH 256/16K 100-QFP
Manufacturer
Renesas Electronics America
Series
M16C/60/63r
Datasheets

Specifications of R5F363AENFA#U0

Core Processor
M16C/60
Core Size
16/32-Bit
Speed
20MHz
Connectivity
EBI/EMI, I²C, SIO, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F363AENFA#U0
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
R5F363AENFA#U0
Manufacturer:
Renesas Electronics America
Quantity:
10 000
M16C/63 Group
REJ09B0510-0100 Rev.1.00 Sep 15, 2009
Page 643 of 836
27.3
27.3.1
Figure 27.2
Figure 27.3
Processing
cycle
Figure 27.3 shows A/D Conversion Timing.
A/D conversion cycle is based on fAD and φ AD. Divide fAD so φ AD conforms the standard frequency.
Figure 27.2 shows fAD and φ AD.
Set the PCKSTP14 bit in the PCLKSTP1 register to 0 (f1 provide enabled) when using the f1 as the
clock source of fAD.
The above figure applies under the following conditions:
fOCO40M
Operations
One-shot mode
φAD = fAD
A/D Conversion Cycle
processing
processing
1 to 2
CKS0: Bit in the ADCON0 register
CKS1: Bit in the ADCON1 register
CKS2, CKS3: Bits in the ADCON2 register
fAD
Start
Start
fAD and φ AD
A/D Conversion Timing
f1
0
1
CKS3
Open-circuit
Open-circuit
charge time
detection
detection
2 φAD
fAD
fAD
1/3
Sampling time
First bit conversion time
15 φAD
1
0
CKS2
40 φAD
42 φAD
Compare
time
Select A/D conversion speed
1/2
Compare
Second
time
bit
1/2
Compare
25 φAD
Third bit
time
1
0
CKS0
1
0
Compare
Tenth bit
CKS1
time
27. A/D Converter
processing
processing
φAD
End
End
2 to 3
fAD

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