MCF5272CVF66 Freescale Semiconductor, MCF5272CVF66 Datasheet - Page 13

• Manufacturer Part Number: MCF5272CVF66
• Description: IC MPU 32BIT 66MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Not Compliant

Paragraph
Number
1.1 MCF5272 Key Features ................................................................................................................. 1-1
1.2 MCF5272 Architecture .................................................................................................................. 1-4
1.3
1.4 MCF5272-Specific Features .......................................................................................................... 1-7
2.1 Features and Enhancements ........................................................................................................... 2-1
2.2 Programming Model ...................................................................................................................... 2-4
Freescale Semiconductor
1.2.1 Version 2 ColdFire Core ..................................................................................................... 1-4
1.2.2 System Integration Module (SIM) ...................................................................................... 1-5
1.2.3 UART Module .................................................................................................................... 1-6
1.2.4 Timer Module ..................................................................................................................... 1-7
1.2.5 Test Access Port ................................................................................................................. 1-7
1.3.1 System Bus Configuration .................................................................................................. 1-7
1.4.1 Physical Layer Interface Controller (PLIC) ....................................................................... 1-7
1.4.2 Pulse-Width Modulation (PWM) Unit ............................................................................... 1-8
1.4.3 Queued Serial Peripheral Interface (QSPI) ........................................................................ 1-8
1.4.4 Universal Serial Bus (USB) Module .................................................................................. 1-8
2.1.1 Decoupled Pipelines ........................................................................................................... 2-1
2.1.2 Debug Module Enhancements ............................................................................................ 2-4
2.2.1 User Programming Model .................................................................................................. 2-4
System Design .............................................................................................................................. 1-7
1.2.2.1 External Bus Interface .......................................................................................... 1-5
1.2.2.2 Chip Select and Wait State Generation ................................................................. 1-5
1.2.2.3 System Configuration and Protection ................................................................... 1-5
1.2.2.4 Power Management .............................................................................................. 1-6
1.2.2.5 Parallel Input/Output Ports ................................................................................... 1-6
1.2.2.6 Interrupt Inputs ..................................................................................................... 1-6
2.1.1.1 Instruction Fetch Pipeline (IFP) ............................................................................ 2-2
2.1.1.2 Operand Execution Pipeline (OEP) ...................................................................... 2-2
2.2.1.1 Data Registers (D0–D7) ....................................................................................... 2-5
2.1.1.2.1 Illegal Opcode Handling .............................................................................. 2-3
2.1.1.2.2 Hardware Multiply/Accumulate (MAC) Unit.............................................. 2-3
2.1.1.2.3 Hardware Divide Unit.................................................................................. 2-4
MCF5272 ColdFire
Table of Contents
®
Integrated Microprocessor User’s Manual, Rev. 3
ColdFire Core
Chapter 1
Chapter 2
Overview
Title
Number
Page
xiii