MCF5272CVF66 Freescale Semiconductor, MCF5272CVF66 Datasheet - Page 221

• Manufacturer Part Number: MCF5272CVF66
• Description: IC MPU 32BIT 66MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Not Compliant

The descriptor controller opens and closes the buffer descriptors. The DMA controller manages the data
transfer. As soon as the DMA channel is initialized, it begins transferring data. An on-board RAM acts as
both a transmit and receive FIFO, and also provides scratch memory for the FEC.
The RAM is the focal point of all data flow in the FEC. The RAM is divided into three sections: transmit
FIFO, receive FIFO, and descriptor controller memory. User data flows to or from the DMA unit from or
to the receive/transmit FIFOs. Transmit data flows from the transmit FIFO into the transmit block. Receive
data flows from the receive block into the receive FIFO.
The user controls the FEC by writing into control registers located in each block. The control and status
registers (CSRs) provide global control (for example, Ethernet reset and enable) and interrupt handling.
The MII block provides a serial channel for the FEC and external physical layer device to pass control and
status information.
The descriptor controller manages data flow in both transmit and receive directions. It is programmed with
microcode to open and close buffer descriptors, control the transmit collision recovery process, and filter
received frame addresses.
The descriptor controller accesses both the transmit and receive descriptor rings through the descriptor
access block. The descriptor access block acts as a dedicated single channel DMA that either reads a
descriptor in external user memory or writes an updated descriptor back into user memory.
11.3
The FEC supports both an MII interface for 10/100 Mbps Ethernet and a seven-wire serial interface for 10
Mbps Ethernet. The interface mode is selected by RCR[MII_MODE]. In MII mode, the 802.3 standard
defines and the FEC module supports 18 signals. These are shown in
Freescale Semiconductor
Transceiver Connection
MCF5272 ColdFire
Transmit clock
Transmit enable
Transmit data
Transmit error
Collision
Carrier sense
Receive clock
Receive enable
Receive data
Receive error
Management channel clock
Management channel serial data
Signal Description
®
Integrated Microprocessor User’s Manual, Rev. 3
Table 11-1. MII Mode
MCF5272 Pin
E_RxD[3:0]
E_TxD[3:0]
E_TxCLK
E_RxCLK
E_RxDV
E_RxER
E_MDIO
E_TxEN
E_TxER
E_MDC
E_CRS
E_COL
Table
11-1.
Ethernet Module
11-3