MCF5272CVF66 Freescale Semiconductor, MCF5272CVF66 Datasheet - Page 164

IC MPU 32BIT 66MHZ 196-MAPBGA

MCF5272CVF66

Manufacturer Part Number
MCF5272CVF66
Description
IC MPU 32BIT 66MHZ 196-MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Datasheets

Specifications of MCF5272CVF66

Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, WDT
Number Of I /o
32
Program Memory Size
16KB (4K x 32)
Program Memory Type
ROM
Ram Size
1K x 32
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Family Name
MCF5xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
66MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
196
Package Type
MA-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Not Compliant

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System Integration Module (SIM)
determine if an internal peripheral is being accessed. MBAR masks specific address spaces using the
address space fields. Attempts to access a masked address space generate an external bus access.
Addresses hitting overlapping memory spaces take the following priority:
Thus, if an overlapping address hits in the SRAM, ROM, or cache, the SIM will not generate a bus cycle,
either externally or to an on-chip peripheral.
Table 6-2
The following example shows how to set the MBAR to location 0x1000_0000 using the D0 register.
Setting MBAR[V] validates the MBAR location. This example assumes all accesses are valid:
move.1 #0x10000001,DO
movec DO,MBAR
6-4
31–16
15–5
Bits
4
3
2
1
0
1. SRAM, ROM, and cache
2. MBAR
3. Chip select
Address
Reset
Field
R/W
Field
UC
UD
describes MBAR fields.
BA
SC
SD
V
31
The MBAR region must be mapped to non-cacheable space.
Base address. Defines the base address for a 64-Kbyte address range
Reserved, should be cleared.
Setting masks supervisor code space in MBAR address range
Setting masks supervisor data space in MBAR address range
Setting masks user code space in MBAR address range
Setting masks user data space in MBAR address range
Valid. Determines whether MBAR settings are valid.
0 MBAR contents are invalid.
1 MBAR contents are valid.
MCF5272 ColdFire
Figure 6-2. Module Base Address Register (MBAR)
W initially through MOVEC; R/W after initialization in supervisor mode
BA
CPU + 0x0C0F initially; MBAR+0x000 after initialization
Table 6-2. MBAR Field Descriptions
®
Integrated Microprocessor User’s Manual, Rev. 3
NOTE
16 15
Undefined
Description
.
5
SC SD UC UD V
4
Attribute Mask Bits
Freescale Semiconductor
3
2
1
0
0

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