MCF5272CVF66 Freescale Semiconductor, MCF5272CVF66 Datasheet - Page 92

• Manufacturer Part Number: MCF5272CVF66
• Description: IC MPU 32BIT 66MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Not Compliant

ColdFire Core
2.7.4
Table 2-15
1
2
3
4
2-24
movem.l
wdebug.l
Opcode
Opcode
movem.l
wddata.l
move.w
move.w
move.w
move.w
n is the number of registers moved by the MOVEM opcode.
PEA execution times are the same for (d16,PC).
PEA execution times are the same for (d8,PC,Xi*SF).
The execution time for STOP is the time required until the processor begins sampling continuously for interrupts.
cpushl
movec
trapf.w
subq.l
subx.l
link.w
trapf.l
pulse
subi.l
sub.l
trapf
stop
unlk
nop
pea
trap
1
lists timings for miscellaneous instructions.
Miscellaneous Instruction Execution Times
<ea>,CCR
<ea>,&list
&list,<ea>
#imm,<ea>
<ea>,SR
Ay,#imm
CCR,Dx
#imm,Dx
SR,Dx
Dy,<ea>
Ry,Rc
#imm
#imm
<ea>
<ea>
<ea>
<ea>
(Ax)
Dy,Dx
<ea>
Ax
Table 2-14. Two-Operand Instruction Execution Times (continued)
MCF5272 ColdFire
Table 2-15. Miscellaneous Instruction Execution Times
2(0/1)
1(0/0)
1(0/0)
1(0/0)
7(0/0)
9(0/1)
3(0/0)
1(0/0)
1(0/0)
1(0/0)
1(0/0)
2(1/0)
1(0/0)
1(0/0)
1(0/0)
Rn
—
—
—
—
—
—
—
—
Rn
—
3(1/1)
3(1/1)
1+n(n/0)
1+n(0/n)
11(0/1)
(An)
2(0/1)
3(1/0)
5(2/0)
—
—
(An)
®
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Integrated Microprocessor User’s Manual, Rev. 3
3(1/1)
3(1/1)
(An)+
—
—
3(1/0)
(An)+
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
–(An)
3(1/1)
3(1/1)
—
—
–(An)
3(1/0)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Effective Address
Effective Address
(d16,An)
3(1/1)
3(1/1)
(d16,An)
1+n(n/0)
1+n(0/n)
2(0/1)
—
—
3(1/0)
5(2/0)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
(d8,An,Xi*SF)
(d8,An,Xi*SF)
4(1/1)
4(1/1)
3(0/1)
—
—
4(1/0)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3
Freescale Semiconductor
(xxx).wl
(xxx).wl
3(1/1)
3(1/1)
2(0/1)
3(1/0)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
#<xxx>
#<xxx>
15(1/2)
3(0/0)
1(0/0)
7(0/0)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4