MCF5272CVF66 Freescale Semiconductor, MCF5272CVF66 Datasheet - Page 8

• Manufacturer Part Number: MCF5272CVF66
• Description: IC MPU 32BIT 66MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Not Compliant

Figure
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viii
The USB “Tiered Star” Topology........................................................................................... 12-2
USB Module Block Diagram.................................................................................................. 12-3
USB Frame Number Register (FNR) .................................................................................... 12-9
USB Frame Number Match Register (FNMR)....................................................................... 12-9
USB Real-Time Frame Monitor Register (RFMR)............................................................... 12-10
USB Real-Time Frame Monitor Match Register (RFMMR)................................................. 12-11
USB Function Address Register (FAR)............................................................................... 12-11
USB Alternate Settings Register (ASR) .............................................................................. 12-12
USB Device Request Data 1 Register (DRR1) ................................................................... 12-13
USB Device Request Data 2 Register (DRR2) ................................................................... 12-13
USB Specification Number Register (SPECR) ................................................................... 12-14
USB Endpoint 0 Status Register (EP0SR).......................................................................... 12-14
USB Endpoint 0 IN Configuration Register (IEP0CFG) ...................................................... 12-15
USB Endpoint 0 OUT Configuration Register ..................................................................... 12-16
USB Endpoint 1–7 Configuration Register.......................................................................... 12-16
USB Endpoint 0 Control Register (EP0CTL)....................................................................... 12-17
USB Endpoint 1-7 Control Register (EPnCTL) ................................................................... 12-20
USB Endpoint 0 Interrupt Mask (EP0IMR)
and General/Endpoint 0 Interrupt Registers (EP0ISR) ....................................................... 12-22
USB Endpoints 1–7 Interrupt Status Registers (EPnISR)................................................... 12-25
USB Endpoint 1-7 Interrupt Mask Registers (EPnIMR) ...................................................... 12-26
USB Endpoint 0-7 Data Registers (EPnDR) ....................................................................... 12-27
USB Endpoint 0-7 Data Present Registers (EPnDPR) ....................................................... 12-28
Example USB Configuration Descriptor Structure .............................................................. 12-29
Recommended USB Line Interface..................................................................................... 12-36
USB Protection Circuit ........................................................................................................ 12-37
PLIC System Diagram........................................................................................................... 13-2
GCI/IDL Receive Data Flow .................................................................................................. 13-3
GCI/IDL B-Channel Receive Data Register Demultiplexing.................................................. 13-4
GCI/IDL Transmit Data Flow ................................................................................................. 13-4
GCI/IDL B Data Transmit Register Multiplexing.................................................................... 13-5
B-Channel Unencoded and HDLC Encoded Data ................................................................ 13-6
D-Channel HDLC Encoded and Unencoded Data. ............................................................... 13-7
D-Channel Contention .......................................................................................................... 13-8
GCI/IDL Loopback Mode ...................................................................................................... 13-9
Periodic Frame Interrupt ..................................................................................................... 13-10
PLIC Internal Timing Signal Routing ................................................................................... 13-12
PLIC Clock Generator ......................................................................................................... 13-12
B1 Receive Data Registers P0B1RR–P3B1RR .................................................................. 13-15
B2 Receive Data Registers P0B2RR – P3B2RR ................................................................ 13-16
D Receive Data Registers P0DRR–P3DRR ....................................................................... 13-16
B1 Transmit Data Registers P0B1TR–P3B1TR.................................................................. 13-17
B2 Transmit Data Registers P0B2TR–P3B2TR.................................................................. 13-17
Transmit Buffer Descriptor (TxBD)..................................................................................... 11-37
MCF5272 ColdFire
List of Figures (Continued)
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Integrated Microprocessor User’s Manual, Rev. 3
Title
Freescale Semiconductor
Number
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