MCF5272CVF66 Freescale Semiconductor, MCF5272CVF66 Datasheet - Page 197

• Manufacturer Part Number: MCF5272CVF66
• Description: IC MPU 32BIT 66MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Not Compliant

Freescale Semiconductor
14–13
12–11
10–8
Bits
6–5
15
7
4
3
2
1
0
BALOC Bank address location. Determines the internal addresses that become SDRAM bank addresses.
SLEEP SLEEP mode. This read-only status bit goes high when setting SDCR[GSL] has taken effect and the
MCAS
Name
REG
GSL
ACT
INIT
INV
—
—
—
Reserved, should be cleared.
Maximum CAS address. Determines which device address output carries the column address msb. For
example, if the SDRAM device has eight column addresses and the data bus is configured for 32 bits, the
column address appears on A[9:2], so the maximum column address is A9. The lsb of the row address is
therefore taken from internal address signal A10 and is used by the SDRAM controller to control address
multiplexing.
00 A7
01 A8
10 A9
11 A10
Reserved, should be cleared.
000Reserved
001A21A20
010A22A21
011A23A22
100A24A23
101A25A24
110Reserved
111Reserved
Go to sleep. Setting GSL powers down the SDRAM and puts it into auto-refresh mode.
Reserved, should be cleared.
Register read data for 66 MHz. Writing a 1 to REG enables pipeline mode for read data access. It forces
the SDRAM controller to register the read data, adding one wait state to single-read accesses and to the
first word read during a burst. REG must be 1 for clock frequencies above 48 MHz to meet input setup timing
for data input (See electrical characteristics timing SD16). The description of INV shows how REG and INV
interact.
Invert clock. Inverts SDRAM clock output for timing refinement.
If REG = 0
0 Do not add wait state for read accesses.
1 Shift SDCLK edge 180
If REG = 1
0 Add wait state for read accesses, all frequencies
1 Invalid, do not use.
SDRAM is powered down. SLEEP is cleared when SDRAM is in auto-refresh mode.
Active. This read-only status bit goes high when the SDRAM controller completes its initialization. ACT is
cleared by writing to SDCR.
Initialization enable. Setting INIT enables initialization of the SDRAM based on other SDCR bit values.
Initialization starts after the first dummy write access to the SDRAM. CSOR7, CSBR7, and SDTR must be
configured before setting INIT.
CAUTION: CSOR7[WAITST] must equal 0x1F when CS7/SDCS is configured for SDRAM.
SDBA1SDBA0
MCF5272 ColdFire
Table 9-7. SDCR Field Descriptions
o
®
Integrated Microprocessor User’s Manual, Rev. 3
Description
SDRAM Controller
9-7