PIC16F1824-I/P Microchip Technology, PIC16F1824-I/P Datasheet - Page 269

• Manufacturer Part Number: PIC16F1824-I/P
• Description: IC PIC MCU 8BIT 14KB FLSH 14PDIP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1824-I/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 11
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 14-DIP (0.300", 7.62mm)
• Processor Series: PIC16F
• Core: PIC
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

25.5.4 SLAVE MODE 10-BIT ADDRESS
This section describes a standard sequence of events
for the MSSP1 module configured as an I
10-bit Addressing mode.
Figure 25-19
description.
This is a step by step process of what must be done by
slave software to accomplish I
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Slave clears SSP1IF.
11. Slave reads the received matching address
12. Slave loads high address into SSP1ADD.
13. Master clocks a data byte to the slave and
14. If SEN bit of SSP1CON2 is set, CKP is cleared
15. Slave clears SSP1IF.
16. Slave reads the received byte from SSP1BUF
17. If SEN is set the slave sets CKP to release the
18. Steps 13-17 repeat for each received byte.
19. Master sends Stop to end the transmission.
 2010 Microchip Technology Inc.
Note: Updates to the SSP1ADD register are not
Note: If the low address does not match, SSP1IF
Bus starts Idle.
Master
SSP1STAT is set; SSP1IF is set if interrupt on
Start detect is enabled.
Master sends matching high address with R/W
bit clear; UA bit of the SSP1STAT register is set.
Slave sends ACK and SSP1IF is set.
Software clears the SSP1IF bit.
Software
SSP1BUF clearing the BF flag.
Slave loads low address into SSP1ADD,
releasing SCL.
Master sends matching low address byte to the
Slave; UA bit is set.
Slave sends ACK and SSP1IF is set.
from SSP1BUF clearing BF.
clocks out the slaves ACK on the 9th SCL pulse;
SSP1IF is set.
by hardware and the clock is stretched.
clearing BF.
SCL.
RECEPTION
allowed until after the ACK sequence.
and UA are still set so that the slave soft-
ware can set SSP1ADD back to the high
address. BF is not set because there is no
match. CKP is unaffected.
sends
is used as a visual reference for this
reads
Start
received
condition;
2
C communication.
address
S
2
C Slave in
bit
from
of
Preliminary
25.5.5 10-BIT ADDRESSING WITH ADDRESS
Reception using 10-bit addressing with AHEN or
DHEN set is the same as with 7-bit modes. The only
difference is the need to update the SSP1ADD register
using the UA bit. All functionality, specifically when the
CKP bit is cleared and SCL line is held low are the
same.
slave in 10-bit addressing with AHEN set.
Figure 25-21
transmitter in 10-bit Addressing mode.
PIC16(L)F1824/1828
Figure 25-20
OR DATA HOLD
shows a standard waveform for a slave
can be used as a reference of a
DS41419B-page 269