PIC16F1824-I/P Microchip Technology, PIC16F1824-I/P Datasheet - Page 286

• Manufacturer Part Number: PIC16F1824-I/P
• Description: IC PIC MCU 8BIT 14KB FLSH 14PDIP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1824-I/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 11
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 14-DIP (0.300", 7.62mm)
• Processor Series: PIC16F
• Core: PIC
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC16(L)F1824/1828
25.6.13.1
During a Start condition, a bus collision occurs if:
a)
b)
During a Start condition, both the SDA and the SCL
pins are monitored.
If the SDA pin is already low, or the SCL pin is already
low, then all of the following occur:
• the Start condition is aborted,
• the BCL1IF flag is set and
• the MSSP1 module is reset to its Idle state
The Start condition begins with the SDA and SCL pins
deasserted. When the SDA pin is sampled high, the
Baud Rate Generator is loaded and counts down. If the
SCL pin is sampled low while SDA is high, a bus colli-
sion occurs because it is assumed that another master
is attempting to drive a data ‘1’ during the Start
condition.
FIGURE 25-33:
DS41419B-page 286
(Figure
SDA or SCL are sampled low at the beginning of
the Start condition
SCL is sampled low before SDA is asserted low
(Figure
SDA
SCL
SEN
BCL1IF
S
SSP1IF
25-32).
25-33).
Bus Collision During a Start
Condition
BUS COLLISION DURING START CONDITION (SDA ONLY)
(Figure
condition if SDA = 1, SCL = 1
Set SEN, enable Start
SDA sampled low before
Start condition. Set BCL1IF.
S bit and SSP1IF set because
SDA = 0, SCL = 1.
25-32).
SDA goes low before the SEN bit is set.
Set BCL1IF,
S bit and SSP1IF set because
SDA = 0, SCL = 1.
Preliminary
SSP1IF and BCL1IF are
cleared by software
If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure
pin, the SDA pin is asserted low at the end of the BRG
count. The Baud Rate Generator is then reloaded and
counts down to zero; if the SCL pin is sampled as ‘0’
during this time, a bus collision does not occur. At the
end of the BRG count, the SCL pin is asserted low.
Note:
SEN cleared automatically because of bus collision.
SSP1 module reset into Idle state.
25-34). If, however, a ‘1’ is sampled on the SDA
The reason that bus collision is not a fac-
tor during a Start condition is that no two
bus masters can assert a Start condition
at the exact same time. Therefore, one
master will always assert SDA before the
other. This condition does not cause a bus
collision because the two masters must be
allowed to arbitrate the first address fol-
lowing the Start condition. If the address is
the same, arbitration must be allowed to
continue into the data portion, Repeated
Start or Stop conditions.
SSP1IF and BCL1IF are
cleared by software
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