PIC16F1824-I/P Microchip Technology, PIC16F1824-I/P Datasheet - Page 322

• Manufacturer Part Number: PIC16F1824-I/P
• Description: IC PIC MCU 8BIT 14KB FLSH 14PDIP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1824-I/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 11
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 14-DIP (0.300", 7.62mm)
• Processor Series: PIC16F
• Core: PIC
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

FIGURE 26-12:
TABLE 26-8:
 2010 Microchip Technology Inc.
APFCON0
BAUDCON
INTCON
PIE1
PIR1
RCREG
RCSTA
SPBRGL
SPBRGH
TXSTA
Legend:
Note 1:
(SCKP = 0)
(SCKP = 1)
(Interrupt)
Note:
TX/CK pin
TX/CK pin
CREN bit
SREN bit
bit SREN
RCIF bit
RCREG
Name
RX/DT
Write to
Read
pin
*
— = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Master Reception.
Page provides register information.
PIC16F/LF1824 only.
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
‘0’
RXDTSEL
TMR1GIE
TMR1GIF
ABDOVF
BRG15
CSRC
SPEN
BRG7
SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER
RECEPTION
Bit 7
GIE
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
SDOSEL
bit 0
BRG14
RCIDL
BRG6
PEIE
ADIE
ADIF
Bit 6
RX9
TX9
(1)
bit 1
SSSEL
TMR0IE
BRG13
SREN
BRG5
TXEN
RCIE
RCIF
Bit 5
—
EUSART Receive Data Register
(1)
bit 2
Preliminary
BRG12
SCKP
CREN
SYNC
BRG4
INTE
Bit 4
TXIE
TXIF
—
bit 3
T1GSEL
SSP1IE
SSP1IF
ADDEN
SENDB
BRG16
BRG11
IOCIE
BRG3
Bit 3
PIC16(L)F1824/1828
bit 4
TXCKSEL
TMR0IF
CCP1IE
CCP1IF
BRG10
BRGH
FERR
BRG2
Bit 2
—
bit 5
TMR2IE
TMR2IF
OERR
BRG1
BRG9
TRMT
WUE
Bit 1
INTF
bit 6
—
TMR1IE
bit 7
TMR1IF
ABDEN
IOCIF
RX9D
BRG0
BRG8
TX9D
Bit 0
DS41419B-page 321
—
Register
on Page
302*
309*
309*
122
308
307
306
93
94
97
‘0’