DSPIC30F6010A-20E/PT Microchip Technology, DSPIC30F6010A-20E/PT Datasheet - Page 131

• Manufacturer Part Number: DSPIC30F6010A-20E/PT
• Description: IC,DSP,16-BIT,CMOS,TQFP,80PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6010A-20E/PT

• Rohs Compliant: YES
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 144KB (48K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-TFQFP
• Package: 80TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 68
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300019 - BOARD DEMO DSPICDEM 80L STARTERXLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC30F007 - MODULE SKT FOR DSPIC30F 80TQFPDM300020 - BOARD DEV DSPICDEM MC1 MOTORCTRL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.6.2
There is a programmable prescaler, with integral
values ranging from 1 to 64, in addition to a fixed
divide-by-2 for clock generation. The Time Quantum
(T
period, and is given by Equation 19-1, where F
F
cleared).
EQUATION 19-1:
19.6.3
This part of the bit time is used to compensate physical
delay times within the network. These delay times
consist of the signal propagation time on the bus line
and the internal delay time of the nodes. The
Propagation Segment can be programmed from 1 T
to
(CiCFG2<2:0>).
19.6.4
The phase segments are used to optimally locate the
sampling of the received bit within the transmitted bit
time. The sampling point is between Phase1 Seg and
Phase2 Seg. These segments are lengthened or short-
ened by re-synchronization. The end of the Phase1
Seg determines the sampling point within a bit period.
The segment is programmable from 1 T
Phase2 Seg provides delay to the next transmitted data
transition. The segment is programmable from 1 T
8 T
Phase1 Seg or the Information Processing Time
(2 T
SEG1PH<2:0> (CiCFG2<5:3>), and Phase2 Seg is
initialized by setting SEG2PH<2:0> (CiCFG2<10:8>).
The following requirement must be fulfilled while setting
the lengths of the Phase Segments:
• Propagation Segment + Phase1 Seg > = Phase2 Seg
© 2008 Microchip Technology Inc.
CY
Q
Note:
Q
) is a fixed unit of time derived from the oscillator
Q
(if the CANCKS bit is set or 4 F
, or it may be defined to be equal to the greater of
8 T
). The Phase1 Seg is initialized by setting bits
Q
T
PRESCALER SETTING
F
CANCKS = 0, then F
7.5 MHz.
PROPAGATION SEGMENT
PHASE SEGMENTS
by
Q
CAN
= 2 ( BRP<5:0> + 1 )/F
setting
must not exceed 30 MHz. If
TIME QUANTUM FOR
CLOCK GENERATION
the
CY
PRSEG<2:0>
CY
must not exceed
CAN
(if CANCKS is
Q
to 8 T
CAN
Q
bits
Q
to
is
Q
.
dsPIC30F6010A/6015
19.6.5
The sample point is the point of time at which the bus
level is read and interpreted as the value of that
respective bit. The location is at the end of Phase1
Seg. If the bit timing is slow and contains many T
possible to specify multiple sampling of the bus line at
the sample point. The level determined by the CAN bus
then corresponds to the result from the majority deci-
sion of three values. The majority samples are taken at
the sample point and twice before with a distance of
T
between sampling three times at the same point or
once at the same point, by setting or clearing the SAM
bit (CiCFG2<6>).
Typically, the sampling of the bit should take place at
about 60-70% through the bit time, depending on the
system parameters.
19.6.6
To compensate for phase shifts between the oscillator
frequencies of the different bus stations, each CAN
controller must be able to synchronize to the relevant
signal edge of the incoming signal. When an edge in
the transmitted data is detected, the logic will compare
the location of the edge to the expected time
(Synchronous Segment). The circuit will then adjust the
values of Phase1 Seg and Phase2 Seg. There are 2
mechanisms used to synchronize.
19.6.6.1
Hard synchronization is only done whenever there is a
recessive to dominant edge during bus Idle, indicating
the start of a message. After hard synchronization, the
bit time counters are restarted with the Synchronous
Segment. Hard synchronization forces the edge which
has caused the hard synchronization to lie within the
synchronization segment of the restarted bit time. If a
hard synchronization is done, there will not be a
resynchronization within that bit time.
19.6.6.2
As a result of re-synchronization, Phase1 Seg may be
lengthened or Phase2 Seg may be shortened. The
amount of lengthening or shortening of the phase
buffer segment has an upper bound known as the
synchronization jump width, and is specified by the
SJW<1:0> bits (CiCFG1<7:6>). The value of the
synchronization jump width will be added to Phase1
Seg
re-synchronization jump
between 1 T
The following requirement must be fulfilled while setting
the SJW<1:0> bits:
• Phase2 Seg > Synchronization Jump Width
Q
/2. The CAN module allows the user to chose
or
subtracted
SAMPLE POINT
SYNCHRONIZATION
Q
Hard Synchronization
Re-synchronization
and 4 T
Q
.
from
width
Phase2
DS70150D-page 131
is
programmable
Seg.
Q
, it is
The