DSPIC30F6010A-20E/PT Microchip Technology, DSPIC30F6010A-20E/PT Datasheet - Page 18

• Manufacturer Part Number: DSPIC30F6010A-20E/PT
• Description: IC,DSP,16-BIT,CMOS,TQFP,80PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6010A-20E/PT

• Rohs Compliant: YES
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 144KB (48K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-TFQFP
• Package: 80TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 68
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300019 - BOARD DEMO DSPICDEM 80L STARTERXLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC30F007 - MODULE SKT FOR DSPIC30F 80TQFPDM300020 - BOARD DEV DSPICDEM MC1 MOTORCTRL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

dsPIC30F6010A/6015
2.3
The dsPIC DSC devices feature a 16/16-bit signed
fractional divide operation, as well as 32/16-bit and
16/16-bit
operations, in the form of single instruction iterative
divides. The following instructions and data sizes are
supported:
• DIVF – 16/16 signed fractional divide
• DIV.sd – 32/16 signed divide
• DIV.ud – 32/16 unsigned divide
• DIV.s – 16/16 signed divide
• DIV.u – 16/16 unsigned divide
TABLE 2-1:
2.4
The DSP engine consists of a high-speed 17-bit x
17-bit multiplier, a barrel shifter, and a 40-bit
adder/subtractor (with two target accumulators, round
and saturation logic).
The dsPIC30F devices have a single instruction flow
which can execute either DSP or MCU instructions.
Many of the hardware resources are shared between
the DSP and MCU instructions. For example, the
instruction set has both DSP and MCU multiply
instructions which use the same hardware multiplier.
The DSP engine also has the capability to perform
inherent accumulator-to-accumulator operations, which
require no additional data. These instructions are ADD,
SUB and NEG.
The DSP engine has various options selected through
various bits in the CPU Core Configuration register
(CORCON), as listed below:
• Fractional or Integer DSP Multiply (IF).
• Signed or Unsigned DSP Multiply (US).
• Conventional or Convergent Rounding (RND).
• Automatic Saturation On/Off for AccA (SATA).
• Automatic Saturation On/Off for AccB (SATB).
• Automatic Saturation On/Off for Writes to Data
• Accumulator Saturation mode Selection
DS70150D-page 18
DIVF
DIV.sd
DIV.s
DIV.ud
DIV.u
Memory (SATDW).
(ACCSAT).
Note:
Divide Support
DSP Engine
signed
For CORCON layout, see Table 3-3.
Instruction
DIVIDE INSTRUCTIONS
and
unsigned
integer
Signed fractional divide: Wm/Wn → W0; Rem → W1
Signed divide: (Wm+1:Wm)/Wn → W0; Rem → W1
Signed divide: Wm/Wn → W0; Rem → W1
Unsigned divide: (Wm+1:Wm)/Wn → W0; Rem → W1
Unsigned divide: Wm/Wn → W0; Rem → W1
divide
The divide instructions must be executed within a
REPEAT loop. Any other form of execution (e.g., a
series of discrete divide instructions) will not function
correctly because the instruction flow depends on
RCOUNT. The divide instruction does not automatically
set up the RCOUNT value, and it must, therefore, be
explicitly and correctly specified in the REPEAT
instruction, as shown in Table 2-1 (REPEAT will execute
the target instruction {operand value + 1} times). The
REPEAT loop count must be set up for 18 iterations of
the DIV/DIVF instruction. Thus, a complete divide
operation requires 19 cycles.
A block diagram of the DSP engine is shown in
Figure 2-2.
TABLE 2-2:
Note:
Instruction
MOVSAC
MPY.N
EDAC
CLR
MAC
MPY
MSC
ED
Function
The divide flow is interruptible. However,
the user needs to save the context as
appropriate.
DSP INSTRUCTION
SUMMARY
© 2008 Microchip Technology Inc.
Algebraic Operation
A = 0
A = (x – y)
A = A + (x – y)
A = A + (x * y)
No change in A
A = x * y
A = – x * y
A = A – x * y
2
2