DSPIC30F6010A-20E/PT Microchip Technology, DSPIC30F6010A-20E/PT Datasheet - Page 161

• Manufacturer Part Number: DSPIC30F6010A-20E/PT
• Description: IC,DSP,16-BIT,CMOS,TQFP,80PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6010A-20E/PT

• Rohs Compliant: YES
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 144KB (48K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-TFQFP
• Package: 80TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 68
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300019 - BOARD DEMO DSPICDEM 80L STARTERXLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC30F007 - MODULE SKT FOR DSPIC30F 80TQFPDM300020 - BOARD DEV DSPICDEM MC1 MOTORCTRL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

If Watchdog Timer is enabled, then the processor will
wake-up from Sleep mode upon WDT time-out. The
Sleep and WDTO Status bits are both set.
21.5.2
In Idle mode, the clock to the CPU is shutdown while
peripherals keep running. Unlike Sleep mode, the clock
source remains active.
Several peripherals have a control bit in each module,
that allows them to operate during Idle.
LPRC fail-safe clock remains active if clock failure
detect is enabled.
The processor wakes up from Idle if at least one of the
following conditions is true:
• on any interrupt that is individually enabled (IE bit
• on any Reset (POR, BOR, MCLR)
• on WDT time-out
Upon wake-up from Idle mode, the clock is re-applied
to the CPU and instruction execution begins
immediately, starting with the instruction following the
PWRSAV instruction.
Any interrupt that is individually enabled (using IE bit)
and meets the prevailing priority level will be able to
wake-up the processor. The processor will process the
interrupt and branch to the ISR. The Idle Status bit in
RCON register is set upon wake-up.
Any Reset, other than POR, will set the Idle Status bit.
On a POR, the Idle bit is cleared.
If Watchdog Timer is enabled, then the processor will
wake-up from Idle mode upon WDT time-out. The Idle
and WDTO Status bits are both set.
Unlike wake-up from Sleep, there are no time delays
involved in wake-up from Idle.
© 2008 Microchip Technology Inc.
is ‘1’) and meets the required priority level
IDLE MODE
dsPIC30F6010A/6015
21.6
The Configuration bits in each device Configuration
register specify some of the device modes and are
programmed by a device programmer, or by using the
In-Circuit Serial Programming™ (ICSP™) feature of the
device. Each device Configuration register is a 24-bit
register, but only the lower 16 bits of each register are
used to hold configuration data. There are six device
Configuration registers available to the user:
1.
2.
3.
4.
5.
6.
7.
The placement of the Configuration bits is automatically
handled when you select the device in your device
programmer. The desired state of the Configuration bits
may be specified in the source code (dependent on the
language tool used), or through the programming
interface. After the device has been programmed, the
application software may read the Configuration bit
values through the table read instructions. For additional
information, please refer to the “dsPIC30F/33F
Programmers Reference Manual” (DS70157) and the
“dsPIC30F Family Reference Manual” (DS70046).
Note 1: If the code protection Configuration Fuse
FOSC (0xF80000): Oscillator Configuration
register
FWDT (0xF80002): Watchdog Timer
Configuration register
FBORPOR (0xF80004): BOR and POR
Configuration register
FBS (0xF80006): Boot Code Segment
Configuration register
FSS (0xF80008): Secure Code Segment
Configuration register
FGS (0xF8000A): General Code Segment
Configuration register
FICD (0xF8000C): FUSE Configuration
Register
2: This device supports an Advanced
Device Configuration Registers
bits (FBS(BSS<2:0>), FSS(SSS<2:0>),
FGS<GCP> and FGS<GWRP>) have
been programmed, an erase of the entire
code-protected device is only possible at
voltages V
implementation
Security. Please refer to the “CodeGuard
Security”
information on how CodeGuard Security
may be used in your application.
DD
chapter
≥ 4.5V.
of
DS70150D-page 161
(DS70180)
CodeGuard™
for