DJLXT386LE.B2 Intel, DJLXT386LE.B2 Datasheet - Page 15

• Manufacturer Part Number: DJLXT386LE.B2
• Manufacturer: Intel

Specifications of DJLXT386LE.B2

• Lead Free Status / RoHS Status: Not Compliant

Datasheet
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply;
2. N/C means “Not Connected”
N4, P4
PBGA
Ball #
N.C.: Not Connected.
Table 1. Pin Assignments and Signal Descriptions (Sheet 5 of 11)
P1
P2
P3
K4
K2
LQFP
Pin #
22
23
24
25
99
26
RDATA0
Symbol
RPOS0/
RNEG0/
RCLK0
TVCC0
BPV0
LOS0
MUX
I/O
DO
DO
DO
DO
DO
DO
DI
S
1
Receive Clock.
Normal Mode:
This pin provides the recovered clock from the signal received at RTIP and
RRING. Under LOS conditions there is a transition from RCLK signal
(derived from the recovered data) to MCLK signal at the RCLK output.
Data Recovery Mode:
If MCLK is High, the clock recovery circuit is disabled and RPOS and
RNEG are internally connected to an EXOR that is fed to the RCLK output
for external clock recovery applications.
RCLK will be in high impedance state if the MCLK pin is Low.
Receive Positive.
Receive Data.
Receive Negative Data.
Bipolar Violation Detect.
Bipolar Mode:
In clock recovery mode these pins act as active high bipolar non return to
zero (NRZ) receive signal outputs. A High signal on RPOS corresponds to
receipt of a positive pulse on RTIP/RRING. A High signal on RNEG
corresponds to receipt of a negative pulse on RTIP/RRING. These signals
are valid on the falling or rising edges of RCLK depending on the CLKE
input.
In Data recovery Mode these pins act as RZ data receiver outputs. The
output polarity is selectable with CLKE (Active High output polarity when
CLKE is High and Active Low Polarity when CLKE is Low).
RPOS and RNEG will go to the high impedance state when the MCLK pin
is Low.
Unipolar Mode:
In uni-polar mode, the LXT386 asserts BPV High if any in-service Line
Code Violation is detected. RDATA acts as the receive data output.
Hardware Mode: During a LOS condition, RPOS and RNEG will remain
active.
Host Mode: RPOS and RNEG will either remain active or insert AIS into
the receive path. Selection is determined by the RAISEN bit in the GCR
register.
Loss of Signal. LOS goes High to indicate a loss of signal, i.e. when the
incoming signal has no transitions for a specified time interval. The LOS
condition is cleared and the output pin returns to Low when the incoming signal
has sufficient number of transitions in a specified time interval. See
Signal Detector” on page
Multiplexed/Non-Multiplexed Select.
When Low the parallel host interface operates in non-multiplexed mode.
When High the parallel host interface operates in multiplexed mode. In
hardware mode tie this unused input low.
Transmit Driver Power Supply. Power supply pin for the port 0 output
driver. TVCC pins can be connected to either a 3.3V or 5V power supply.
Refer to the Transmitter description.
QUAD T1/E1/J1 Transceiver — LXT386
25.
Description
“Loss of
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