DJLXT386LE.B2 Intel, DJLXT386LE.B2 Datasheet - Page 5

• Manufacturer Part Number: DJLXT386LE.B2
• Manufacturer: Intel

Specifications of DJLXT386LE.B2

• Lead Free Status / RoHS Status: Not Compliant

Tables
Datasheet
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E1, G.703 Mask Templates................................................................................. 77
T1, T1.102 Mask Templates................................................................................ 78
LXT386 Jitter Tolerance Performance ................................................................ 79
Jitter Transfer Performance................................................................................. 80
Output Jitter for CTR12/13 applications .............................................................. 81
60 Plastic Ball Grid Array (PBGA) Package Dimensions .................................... 82
100 Pin Low Quad Flat Packages (LQFP) Dimensions ...................................... 83
Sample LQFP Non-RoHS Package - Intel
Sample LQFP RoHS Package - Intel
Order Matrix ........................................................................................................86
Pin Assignments and Signal Descriptions ...........................................................11
Line Length Equalizer Inputs............................................................................... 28
Jitter Attenuation Specifications .......................................................................... 32
Operation Mode Summary .................................................................................. 38
Microprocessor Parallel Interface Selection ........................................................ 39
Serial and Parallel Port Register Addresses ....................................................... 43
Register Bit Names ............................................................................................. 43
ID Register, ID (00H)........................................................................................... 44
Analog Loopback Register, ALOOP (01H).......................................................... 44
Remote Loopback Register, RLOOP (02H) ........................................................ 45
TAOS Enable Register, TAOS (03H) ..................................................................45
LOS Status Monitor Register, LOS (04H) ...........................................................45
DFM Status Monitor Register, DFM (05H) .......................................................... 45
LOS Interrupt Enable Register, LIE (06H) ...........................................................45
DFM Interrupt Enable Register, DIE (07H).......................................................... 45
LOS Interrupt Status Register, LIS (08H)............................................................ 46
DFM Interrupt Status Register, DIS (09H)...........................................................46
Software Reset Register, RES (0AH)..................................................................46
Performance Monitoring Register, MON (0BH)................................................... 46
Digital Loopback Register, DL (0CH) ..................................................................46
LOS/AIS Criteria Register, LCS (0DH) ................................................................ 46
Automatic TAOS Select Register, ATS (0EH)..................................................... 47
Global Control Register, GCR (0FH)................................................................... 47
Pulse Shaping Indirect Address Register, PSIAD (10H) ..................................... 48
Pulse Shaping Data Register, PSDAT (11H) ...................................................... 48
Output Enable Register, OER (12H) ................................................................... 48
AIS Status Monitor Register, AIS (13H) .............................................................. 48
AIS Interrupt Enable Register, AISIE (14H) ........................................................ 49
AIS Interrupt Status Register, AISIS (15H) ......................................................... 49
TAP State Description ......................................................................................... 51
Device Identification Register (IDR) .................................................................... 56
Analog Port Scan Register – ASR.......................................................................57
Instruction Register – IR...................................................................................... 58
Absolute Maximum Ratings................................................................................. 59
Recommended Operating Conditions ................................................................. 59
DC Characteristics .............................................................................................. 60
E1 Transmit Transmission Characteristics.......................................................... 61
®
LXT386 Transceiver............................... 84
QUAD T1/E1/J1 Transceiver — LXT386
®
LXT386 Transceiver ....................... 84
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