DJLXT386LE.B2 Intel, DJLXT386LE.B2 Datasheet - Page 4

• Manufacturer Part Number: DJLXT386LE.B2
• Manufacturer: Intel

Specifications of DJLXT386LE.B2

• Lead Free Status / RoHS Status: Not Compliant

LXT386 — QUAD T1/E1/J1 Transceiver
6.0
7.0
8.0
9.0
Figures
4
5.3
5.4
5.5
Test Specifications
6.1
Mechanical Specifications
7.1
Product Ordering Information
Package Information
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
TAP Controller..................................................................................................... 51
JTAG Register Description.................................................................................. 53
5.4.1
Device Identification Register (IDR) .................................................................... 56
5.5.1
5.5.2
5.5.3
Recommendations and Specifications ................................................................ 81
Top Label Markings............................................................................................. 84
LXT386 Block Diagram ......................................................................................... 7
LXT386 Detailed Block Diagram ........................................................................... 8
LXT386 Low-Profile Quad Flat Package (LQFP) 100 Pin Assignments ............... 9
LXT386 Plastic Ball Grid Array (PBGA) 160 Ball Assignments........................... 10
Pullup Resistor to RESET ................................................................................... 23
50% AMI Encoding.............................................................................................. 27
External Transmit/Receive Line Circuitry ............................................................ 31
Jitter Attenuator Loop .......................................................................................... 33
Analog Loopback ................................................................................................ 34
Digital Loopback.................................................................................................. 34
Remote Loopback ............................................................................................... 35
TAOS Data Path ................................................................................................. 36
TAOS with Analog Loopback .............................................................................. 36
Serial Host Mode Timing ..................................................................................... 42
LXT386 JTAG Architecture ................................................................................. 50
JTAG State Diagram ........................................................................................... 52
Analog Test Port Application ............................................................................... 58
Transmit Clock Timing Diagram .......................................................................... 65
Receive Clock Timing Diagram ........................................................................... 66
JTAG Timing ....................................................................................................... 67
Non-Multiplexed Intel Mode Read Timing ........................................................... 68
Multiplexed Intel Read Timing ............................................................................. 69
Non-Multiplexed Intel Mode Write Timing ........................................................... 70
Multiplexed Intel Mode Write Timing ................................................................... 71
Non-Multiplexed Motorola Mode Read Timing .................................................... 72
Multiplexed Motorola Mode Read Timing............................................................ 73
Non-Multiplexed Motorola Mode Write Timing .................................................... 74
Multiplexed Motorola Mode Write Timin .............................................................. 75
Serial Input Timing .............................................................................................. 76
Serial Output Timing ........................................................................................... 76
Boundary Scan Register (BSR).............................................................. 53
Bypass Register (BYR) .......................................................................... 56
Analog Port Scan Register (ASR) .......................................................... 57
Instruction Register (IR) ......................................................................... 58
.................................................................................................. 59
............................................................................................... 86
................................................................................... 82
............................................................................. 85
Datasheet