DJLXT386LE.B2 Intel, DJLXT386LE.B2 Datasheet - Page 66

• Manufacturer Part Number: DJLXT386LE.B2
• Manufacturer: Intel

Specifications of DJLXT386LE.B2

• Lead Free Status / RoHS Status: Not Compliant

LXT386 — QUAD T1/E1/J1 Transceiver
66
Clock recovery capture range
Receive clock duty cycle
Receive clock pulse width
Receive clock pulse width Low time
Receive clock pulse width High time
Rise/fall time
RPOS/RNEG pulse width (MCLK=H)
RPOS/RNEG to RCLK rising setup time
RCLK Rising to RPOS/RNEG hold time
Delay time between RPOS/RNEG and RCLK
1. RCLK duty cycle widths will vary depending on extent of received pulse jitter displacement. Maximum and minimum RCLK
2. Clock recovery is disabled in this mode.
3. If MCLK = H the receive PLLs are replaced by a simple EXOR circuit.
4. For all digital outputs.
duty cycles are for worst case jitter conditions (0.2UI displacement for E1 per ITU G.823).
Table 44. Receive Timing Characteristics
Figure 19. Receive Clock Timing Diagram
RPOS
RNEG
RPOS
RNEG
RCLK
4
Parameter
1
1
CLKE = 0
CLKE = 1
2
tPWH
tSUR
E1
T1
E1
T1
E1
T1
E1
T1
E1
T1
E1
T1
E1
T1
tPW
Tpwdl
Tpwdl
Tpwh
Tpwh
Rckd
Sym
Tpwl
Tpwl
Tpw
Tpw
Tsur
Thr
Tr
–
–
–
tPWL
tSUR
tHR
Min
447
583
203
259
203
259
200
250
200
200
200
200
40
20
–
–
–
±180
Typ
±80
488
648
244
324
244
324
244
324
244
324
244
324
50
–
–
Max
529
713
285
389
285
389
300
400
60
–
–
–
–
–
–
–
5
tHR
Unit
ppm
ppm
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
Relative to
nominal frequency
MCLK = ±100
ppm
@ CL=15 pF
MCLK = H
Test Condition
Datasheet
3