DJLXT386LE.B2 Intel, DJLXT386LE.B2 Datasheet - Page 49

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DJLXT386LE.B2

Manufacturer Part Number
DJLXT386LE.B2
Description
Manufacturer
Intel
Datasheet

Specifications of DJLXT386LE.B2

Lead Free Status / RoHS Status
Not Compliant
Datasheet
1. On power-up all the register bits are set to “0”.
1. On power-up all the register bits are set to “0”.
Bit
Bit
3-0
7-4
3-0
Table 28. AIS Interrupt Enable Register, AISIE (14H)
Table 29. AIS Interrupt Status Register, AISIS (15H)
1
1
AISIE3-AISIE0
AISIS3-AISIS0
Name
Name
-
Transceiver 3-0 AIS interrupts are enabled by writing a “1” to the respective bit.
Write “0” to these positions for normal operation.
These bits are set to “1” every time a AIS status change has occurred since the last clear
interrupt in transceivers 3-0 respectively.
QUAD T1/E1/J1 Transceiver — LXT386
Function
Function
49

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