DJLXT386LE.B2 Intel, DJLXT386LE.B2 Datasheet - Page 20

• Manufacturer Part Number: DJLXT386LE.B2
• Manufacturer: Intel

Specifications of DJLXT386LE.B2

• Lead Free Status / RoHS Status: Not Compliant

LXT386 — QUAD T1/E1/J1 Transceiver
20
A6, A9
B: 1, 2, 3, 6,
9, 12, 13, 14
C6, C9
D: 1, 2, 3, 6,
9, 12, 13, 14
G4, G11
H4, H11
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply;
2. N/C means “Not Connected”
PBGA
Ball #
N.C.: Not Connected.
Table 1.
N/C
E13
2
11, 65, 66,
5, 7, 10,
Pin Assignments and Signal Descriptions (Sheet 10 of 11)
LQFP
Pin #
100
84
74
Symbol
RESET
CLKE
GND
I/O
DI
DI
S
1
Clock Edge Select. In clock recovery mode, setting CLKE High causes
RDATA or RPOS and RNEG to be valid on the falling edge of RCLK and
SDO to be valid on the rising edge of SCLK. Setting CLKE Low makes
RDATA or RPOS and RNEG to be valid on the rising edge of RCLK and
SDO to be valid on the falling edge of SCLK. In Data recovery Mode,
RDATA or RPOS/RNEG are active High output polarity when CLKE is
High and active low polarity when CLKE is Low.
Reset Input. (Added in Revision B1) In either hardware mode or software
mode, setting RESET low will begin to initialize the LXT386 and freeze the
device until set high. One microsecond after setting RESET high,
initialization will complete and the LXT386 will be ready for normal
operation. For Revision B1 only, the device requires a pull up resistor to
VCC at this pin between 1 and 10 kohms in value. It is not necessary to
retain the pull up resistor for any other revision. Please refer to the section
on Reset Operation for more information. The BGA package does not
have this pin feature.
Power Supply Ground. Connect all pins to power supply ground.
CLKE
High
Low
RPOS/RNEG
RCLK
RCLK
Description
SCLK
SCLK
SDO
Datasheet