DJLXT386LE.B2 Intel, DJLXT386LE.B2 Datasheet - Page 47

• Manufacturer Part Number: DJLXT386LE.B2
• Manufacturer: Intel

Specifications of DJLXT386LE.B2

• Lead Free Status / RoHS Status: Not Compliant

Datasheet
1. On power-on reset the register is set to “0”.
2. This feature is not available in data recovery and line driver mode (MCLK= High and TCLK = High)
1. On power-on reset the register is set to “0”.
Bit
Bit
3-0
7-4
Table 22. Automatic TAOS Select Register, ATS (0EH)
Table 23. Global Control Register, GCR (0FH)
0
1
2
3
4
5
6
7
1
1
ATS3-ATS0
RAISEN
JASEL0
JASEL1
CODEN
FIFO64
Name
Name
JACF
CDIS
-
-
These bits determine the jitter attenuator position:
This bit determines the jitter attenuator low limit 3dB corner frequency. Refer to the Jitter
Attenuator specifications for details
This bit determines the jitter attenuator FIFO depth:
0 = 32 bit
1 = 64 bit
This bit selects the zero suppression code for unipolar operation mode:
0 = B8ZS/HDB3 (T1/E1 respectively)
1 = AMI
This bit controls enables/disables the short circuit protection feature:
0 = enabled
1 = disabled
This bit controls automatic AIS insertion in the receive path when LOS occurs:
0 = Receive AIS insertion disabled on LOS
1 = RPOS/RNEG = AIS on LOS
Note: this feature is not available in data recovery mode (MCLK=High). Disable AIS
interrupts when changing this bit value to prevent inadvertent interrupts.
Reserved.
Setting a bit to “1” enables automatic TAOS generation whenever a LOS condition is
detected in the respective transceiver.
Write “0” to these positions for normal operation.
JASEL0
1
1
0
JASEL1
0
1
x
(Table 41 on page
QUAD T1/E1/J1 Transceiver — LXT386
Transmit Path
Receive Path
Function
Function
JA Position
Disabled
64).
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