DJLXT386LE.B2 Intel, DJLXT386LE.B2 Datasheet - Page 19

• Manufacturer Part Number: DJLXT386LE.B2
• Manufacturer: Intel

Specifications of DJLXT386LE.B2

• Lead Free Status / RoHS Status: Not Compliant

Datasheet
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply;
2. N/C means “Not Connected”
PBGA
Ball #
N.C.: Not Connected.
Table 1. Pin Assignments and Signal Descriptions (Sheet 9 of 11)
H12
G13
H13
G12
F14
F13
F12
E14
J11
F11
1
LQFP
Pin #
98
76
77
72
71
69
73
70
83
MOT/INTL/
CODEN
Symbol
JASEL
TRST
TMS
TDO
TCK
CS/
AT2
AT1
TDI
OE
DI
DI
I/O
AO
DO
DI
DI
AI
DI
DI
DI
DI
1
Chip Select/Jitter Attenuator Select.
Host Mode
This active Low input is used to access the serial/parallel interface. For
each read or write operation, CS must transition from High to Low, and
remain Low.
Hardware Mode
This input determines the Jitter Attenuator position in the data path:
Motorola/Intel/Codec Enable Select.
Host Mode:
When Low, the host interface is configured for Motorola microcontrollers.
When High, the host interface is configured for Intel microcontrollers.
Hardware Mode:
This pin determines the line encode/decode selection when in un-
ipolar mode:
When Low, B8ZS/HDB3 encoders/decoders are enabled for T1/E1
respectively. When High, enables AMI encoder/decoder (transparent
mode).
JTAG Analog Output Test Port 2.
JTAG Analog Input Test Port 1.
JTAG Controller Reset. Input is used to reset the JTAG controller. TRST
is pulled up internally and may be left disconnected.
JTAG Test Mode Select.
Sampled on rising edge of TCK. TMS is pulled up internally and may be
left disconnected.
JTAG Clock. Clock input for JTAG. Connect to GND when not used.
JTAG Data Output. Test Data Output for JTAG. Used for reading all
serial configuration and test data from internal test logic. Updated on
falling edge of TCK.
JTAG Data Input. Test Data input for JTAG. Used for loading serial
instructions and data into internal test logic. Sampled on rising edge of
TCK. TDI is pulled up internally and may be left disconnected.
Output Driver Enable. If this pin is asserted Low all analog driver outputs
immediately enter a high impedance mode to support redundancy
applications without external mechanical relays. All other internal circuitry
stays active. In software mode, TTIP and TRING can be tristated on a
port-by-port basis by writing a ‘1’ to the OEx bit in the Output Enable
Register (OER).
JASEL
H
L
Z
Transmit path
Receive path
Disabled
QUAD T1/E1/J1 Transceiver — LXT386
Used to control the test logic state machine.
Description
JA Position
19