DJLXT386LE.B2 Intel, DJLXT386LE.B2 Datasheet - Page 36

• Manufacturer Part Number: DJLXT386LE.B2
• Manufacturer: Intel

Specifications of DJLXT386LE.B2

• Lead Free Status / RoHS Status: Not Compliant

LXT386 — QUAD T1/E1/J1 Transceiver
3.7.4
36
Figure 12. TAOS Data Path
Figure 13. TAOS with Analog Loopback
Transmit All Ones (TAOS)
In Hardware mode, the TAOS mode is set by pulling TCLK High for more than 16 MCLK cycles.
In software mode, TAOS mode is set by asserting the corresponding bit in the TAOS Register. In
addition, automatic ATS insertion (in case of LOS) may be set using the ATS Register.
Note: The TAOS generator uses MCLK as a timing reference, therefore TAOS doesn’t work in data
recovery mode. In order to assure that the output frequency is within specification limits, MCLK
must have the applicable stability. DLOOP does not function with TAOS active.
RNEG
MCLK
TNEG
RPOS
TPOS
RCLK
TCLK
TPOS
TNEG
TCLK
RPOS
RNEG
MCLK
RCLK
* If Enabled
* If Enabled
TAOS mode
TAOS Mode
JA*
JA*
Recovery
Timing &
Control
Timing
Recovery
Timing &
Control
Timing
TTIP
TRING
(ALL 1's)
RTIP
RRING
TTIP
TRING
(ALL 1's)
RTIP
RRING
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