DJLXT386LE.B2 Intel, DJLXT386LE.B2 Datasheet - Page 67

• Manufacturer Part Number: DJLXT386LE.B2
• Manufacturer: Intel

Specifications of DJLXT386LE.B2

• Lead Free Status / RoHS Status: Not Compliant

Datasheet
Cycle time
J-TMS/J-TDI to J-TCK rising edge time
J-CLK rising to J-TMS/L-TDI hold time
J-TCLK falling to J-TDO valid
Address setup time to latch
Valid address latch pulse width
Latch active to active read setup time
Chip select setup time to active read
Chip select hold time from inactive read
Address hold time from inactive ALE
Active read to data valid delay time
Address setup time to RD inactive
Address hold time from RD inactive
Inactive read to data tri-state delay time
Valid read signal pulse width
Inactive read to inactive INT delay time
Active chip select to RDY delay time
Active ready Low time
Inactive ready to tri-state delay time
1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing.
2. C
Table 45. JTAG Timing Characteristics
Figure 20. JTAG Timing
Table 46. Intel Mode Read Timing Characteristics
L
= 100pF on D0-D7, all other outputs are loaded with 50pF.
TMS
TDO
TCK
TDI
Parameter
Parameter
2
tSUR
Tdod
Sym
Tcyc
Tsut
Tht
Tdrdy
Thcsr
Tvrdy
Trdyz
Tscsr
Thalr
Sym
Tsalr
Tprd
Thar
Tzrd
Tvrd
Tsar
Tint
Tslr
tHT
Tvl
Min
200
50
50
-
Min
10
30
10
10
60
0
0
5
1
5
3
–
0
–
–
tCYC
Typ
tDOD
-
-
-
-
Typ
QUAD T1/E1/J1 Transceiver — LXT386
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1
Max
50
-
-
-
Max
50
35
10
12
40
–
–
–
–
–
–
–
–
3
Unit
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test Conditions
Test Conditions
67