NH82801DB S L8DE Intel, NH82801DB S L8DE Datasheet - Page 132

• Manufacturer Part Number: NH82801DB S L8DE
• Manufacturer: Intel

Specifications of NH82801DB S L8DE

• Lead Free Status / RoHS Status: Compliant

Functional Description
5.11.1.4
5.11.1.5
5.11.1.6
5.11.2
5.11.2.1
132
Table 5-31. NMI Sources
Table 5-32. DP Signal Differences
NMI
Non-Maskable Interrupts (NMIs) can be generated by several sources, as described in
STPCLK# and CPUSLP# Signals
The ICH4 power management logic controls these active-low signals. Refer to
more information on the functionality of these signals.
CPUPWRGOOD Signal
This signal is connected to the processor’s PWRGOOD input. This is an open-drain output signal
(external pull-up resistor required) that represents a logical AND of the ICH4’s PWROK and
VRMPWRGD signals.
Dual-Processor Designs
Signal Differences
In dual-processor (DP) designs, some of the processor signals are unused or used differently than
for uniprocessor designs.
SERR# goes active (either internally, externally
via SERR# signal, or via message from the MCH)
IOCHK# goes active via SERIRQ# stream
(ISA system Error)
A20M# / A20GATE
STPCLK#
FERR# / IGNNE#
Signal
Cause of NMI
Generally not used, but still supported by Intel
Used for S1 State as well as preparation for entry to S3–S5
Also allows for THERM# based throttling (not via ACPI control methods).
Should be connected to both processors.
Generally not used, but still supported by ICH4.
Can instead be routed to generate an SCI, through the
NMI2SCI_EN bit (Device 31:Function 0, offset 4E, bit 11).
Can instead be routed to generate an SCI, through the
NMI2SCI_EN bit (Device 31:Function 0, offset 4E, bit 11).
Difference
Intel
Comment
®
®
ICH4.
82801DB ICH4 Datasheet
Section 5.12
Table
for
5-31.