NH82801DB S L8DE Intel, NH82801DB S L8DE Datasheet - Page 153

• Manufacturer Part Number: NH82801DB S L8DE
• Manufacturer: Intel

Specifications of NH82801DB S L8DE

• Lead Free Status / RoHS Status: Compliant

5.12.12
5.12.12.1
Intel
®
82801DB ICH4 Datasheet
Desktop APM Power Management
Legacy Power Management Theory of Operation
Instead of relying on ACPI software, legacy power management uses BIOS and various hardware
mechanisms. ICH4 has a greatly simplified method for legacy power management compared with
previous generations (e.g., the PIIX4).
The scheme relies on the concept of detecting when individual subsystems are idle, detecting when
the whole system is idle, and detecting when accesses are attempted to idle subsystems.
However, the OS is assumed to be at least APM enabled. Without APM calls, there is no quick way
to know when the system is idle between keystrokes. The ICH4 does not support the burst modes
found in previous components (e.g., the PIIX4).
The ICH4 has a timer that, when enabled by the 1MIN_EN bit in the SMI Control and Enable
register, generates an SMI# once per minute. The SMI handler can check for system activity by
reading the DEVACT_STS register. If none of the system bits are set, the SMI handler can
increment a software counter. When the counter reaches a sufficient number of consecutive
minutes with no activity, the SMI handler can then put the system into a lower power state.
If there is activity, various bits in the DEVACT_STS register will be set. Software clears the bits by
writing a 1 to the bit position.
The DEVACT_STS register allows for monitoring various internal devices, or Super I/O devices
(SP, PP, FDC) on LPC or PCI, keyboard controller accesses, or audio functions on LPC or PCI.
Other PCI activity can be monitored by checking the PCI interrupts.
Functional Description
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