NH82801DB S L8DE Intel, NH82801DB S L8DE Datasheet - Page 152

• Manufacturer Part Number: NH82801DB S L8DE
• Manufacturer: Intel

Specifications of NH82801DB S L8DE

• Lead Free Status / RoHS Status: Compliant

Functional Description
5.12.10.4
5.12.11
152
Table 5-49. Intel
Controlling Leakage and Power Consumption during Low-Power
States
To control leakage in the system, various signals tri-state or go low during some low-power states.
General principles:
Based on the above principles, the following measures are taken:
Clock Generators
The clock generator is expected to provide the frequencies shown in
AC_BIT_CLK
•
•
•
•
LAN_CLK
APICCLK
Domain
PCICLK
CLK66
CLK48
CLK14
All signals going to powered down planes (either internally or externally) must be either tri-
stated or driven low.
Signals with pull-up resistors should not be low during low-power states. This is to avoid the
power consumed in the pull-up resistor.
Buses should be halted (and held) in a known state to avoid a floating input (perhaps to some
other device). Floating inputs can cause extra power consumption.
During S3 (STR), all signals attached to powered down planes will be tri-stated or driven low.
Clock
®
ICH4 Clock Inputs
14.318 MHz
12.288 MHz
Frequency
16.67 MHz
or 33 MHz
66 MHz
33 MHz
48 MHz
50 MHz
0.8 to
Main Clock
Main Clock
Main Clock
Main Clock
Main Clock
Generator
Generator
Generator
Generator
Generator
Connect
Source
AC ’97
Codec
LAN
Should be running in all Cx states. Stopped in S3 ~ S5 based on
SLP_S3# assertion.
Free-running PCI Clock to ICH4. Stopped in S3 ~ S5 based on
SLP_S3# assertion.
Used by USB controllers. Stopped in S3 ~ S5 based on
SLP_S3# assertion.
Used by ACPI timers. Stopped in S3 ~ S5 based on SLP_S3#
assertion.
AC-link. Control policy is determined by the clock source.
Used for ICH4-processor interrupt messages. Should be
running in C0, C1 and C2. Stopped in S3 ~ S5 based on
SLP_S3# assertion.
LAN Connect link. Control policy is determined by the clock
source.
Usage
Intel
Table
®
82801DB ICH4 Datasheet
5-49.