NH82801DB S L8DE Intel, NH82801DB S L8DE Datasheet - Page 223

• Manufacturer Part Number: NH82801DB S L8DE
• Manufacturer: Intel

Specifications of NH82801DB S L8DE

• Lead Free Status / RoHS Status: Compliant

5.18.7.1
Intel
®
Table 5-93. Slave Write Cycle Format
Table 5-94. Slave Write Registers
82801DB ICH4 Datasheet
Format of Slave Write Cycle
The external master performs Byte Write commands to the ICH4 SMBus Slave interface. The
“Command” field (bits 11
(bits 20
The Write Cycle format is shown in
registers.
NOTE: The external microcontroller is responsible to make sure that it does not update the contents of the data
11–18
20–27
Bits
2–8
10
19
28
29
1
9
Register
9–FFh
1–3
6–7
–
byte registers until they have been read by the system processor. The ICH4 will overwrite the old value
with any new value received. A race condition is possible where the new value is being written to the
register just at the time it is being read. ICH4 will not attempt to cover this race condition
(i.e., unpredictable results in this case).
0
4
5
8
27) indicate the value that should be written to that register.
Start Condition
Slave Address - 7 bits
Write
ACK
Command
ACK
Register Data
ACK
Stop
Description
Command Register. See
Reserved
Data Message Byte 0
Data Message Byte 1
Reserved
Frequency Straps will be written on bits 3:0. Bits 7:4 should be 0, but will be ignored.
Reserved
–
18) indicate which register is being accessed. The Data field
External Microcontroller
External Microcontroller
External Microcontroller Always 0
Intel
External Microcontroller
ICH4
External Microcontroller See
ICH4
External Microcontroller
®
Table
ICH4
Driven by
Table 5-95
5-93.
Table 5-94
for legal values written to this register.
Function
Must match value in Receive Slave Address
register
This field indicates which register will be
accessed.
See
Table 5-94
Table 5-94
provides the values associated with the
below for the register definitions
below for the register definitions
Comment
Functional Description
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