NH82801DB S L8DE Intel, NH82801DB S L8DE Datasheet - Page 428

• Manufacturer Part Number: NH82801DB S L8DE
• Manufacturer: Intel

Specifications of NH82801DB S L8DE

• Lead Free Status / RoHS Status: Compliant

EHCI Controller Registers (D29:F7)
12.1.26
12.1.27
428
LEG_EXT_CAP—USB EHCI Legacy Support Extended
Capability Register (USB EHCI—D29:F7)
Address Offset:
Default Value:
Power Well:
LEG_EXT_CS—USB EHCI Legacy Support Extended
Control / Status Register (USB EHCI—D29:F7)
Address Offset:
Default Value:
Power Well:
31:25
23:17
28:22
15:8
Bit
7:0
Bit
24
16
31
30
29
21
20
Reserved — RO. Hardwired to 00h
HC OS Owned Semaphore — R/W. System software sets this bit to request ownership of the EHCI
controller. Ownership is obtained when this bit reads as 1 and the HC BIOS Owned Semaphore bit
reads as clear.
Reserved — RO. Hardwired to 00h
HC BIOS Owned Semaphore — R/W. The BIOS sets this bit to establish ownership of the EHCI
controller. System BIOS will clear this bit in response to a request for ownership of the EHCI
controller by system software.
Next EHCI Capability Pointer — RO. A value of 00h indicates that there are no EHCI Extended
Capability structures in this device.
Capability ID — RO. A value of 01h indicates that this EHCI Extended Capability is the Legacy
Support Capability.
SMI on BAR —R/WC.
0 = Software clears this bit by writing a 1 to this bit location.
1 = This bit is set to 1 whenever the Base Address Register (BAR) is written.
SMI on PCI Command — R/WC.
0 = Software clears this bit by writing a 1 to this bit location.
1 = This bit is set to 1 whenever the PCI Command Register is written.
SMI on OS Ownership Change — R/WC.
0 = Software clears this bit by writing a 1 to this bit location.
1 = HC OS Owned Semaphore bit in the USB EHCI Legacy Support Extended Capability register
Reserved — RO. Hardwired to 00h
SMI on Async Advance — RO. Shadow bit of the Interrupt on Async Advance bit in the EHCI_STS
register.
NOTE: To clear this bit system software must write a 1 to the Interrupt on Async Advance bit in the
SMI on Host System Error — RO. Shadow bit of Host System Error bit in the EHCI_STS register.
NOTE: To clear this bit system software must write a 1 to the Host System Error bit in the
transitioned from 1-to-0 or 0-to-1.
EHCI_STS register.
EHCI_STS register.
Suspend
Suspend
68
00000001h
6C
00000000h
–
–
6Bh
6Fh
Description
Description
Attribute:
Size:
Attribute:
Size:
R/W, RO
32 bits
R/W, R/WC, RO
32 bits
Intel
®
82801DB ICH4 Datasheet