NH82801DB S L8DE Intel, NH82801DB S L8DE Datasheet - Page 495

• Manufacturer Part Number: NH82801DB S L8DE
• Manufacturer: Intel

Specifications of NH82801DB S L8DE

• Lead Free Status / RoHS Status: Compliant

15.1.4
15.1.5
15.1.6
Intel
®
82801DB ICH4 Datasheet
PCISTA—Device Status Register (Modem—D31:F6)
Address Offset:
Default Value:
Lockable:
PCISTA is a 16-bit status register. Refer to the PCI 2.2 specification for complete details on each
bit.
RID—Revision Identification Register (Modem—D31:F6)
Address Offset:
Default Value:
Lockable:
PI—Programming Interface Register (Modem—D31:F6)
Address Offset:
Default Value:
Lockable:
10:9
Bit
3:0
15
14
13
12
11
8
7
6
5
4
7:0
Bit
7:0
Bit
Detected Parity Error (DPE) — RO. Not implemented. Hardwired to 0.
Signaled System Error (SSE) — RO. Not implemented. Hardwired to 0.
Master Abort Status (MAS) — R/WC.
0 = Software clears this bit by writing a 1 to the bit position.
1 = Bus Master AC ‘97 interface function, as a master, generates a master abort.
Reserved. Read as 0.
Signaled Target Abort (STA) — RO. Not implemented. Hardwired to 0.
DEVSEL# Timing Status (DEV_STS) — RO. This 2-bit field reflects the ICH4's DEVSEL# timing
parameter. These read only bits indicate the ICH4's DEVSEL# timing when performing a positive
decode.
Data Parity Error Detected (DPED) — RO. Not implemented. Hardwired to 0.
Fast Back to Back Capable (FB2BC) — RO. Hardwired to 1. This bit indicates that the ICH4 as a
target is capable of fast back-to-back transactions.
User Definable Features (UDF) — RO. Not implemented. Hardwired to 0.
66 MHz Capable (66MHZ_CAP) — RO. Hardwired to 0.
Capabilities List (CAP_LIST) — RO. This field indicates that the controller contains a capabilities
pointer list. The first item is pointed to by looking at configuration offset 34h.
Reserved
Revision Identification Value — RO. Refer to the ICH4 Specification Update for the value of the
Revision ID Register.
Programming Interface — RO.
06
0290h
No
08h
See Bit Description
No
09h
00h
No
–
07h
Description
AC ’97 Modem Controller Registers (D31:F6)
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
R/WC, RO
16 bits
Core
RO
8 Bits
Core
RO
8 bits
Core
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