NH82801DB S L8DE Intel, NH82801DB S L8DE Datasheet - Page 475

• Manufacturer Part Number: NH82801DB S L8DE
• Manufacturer: Intel

Specifications of NH82801DB S L8DE

• Lead Free Status / RoHS Status: Compliant

14.1.15
T
14.1.16
14.1.17
Intel
®
82801DB ICH4 Datasheet
CAP_PTR—Capabilities Pointer Register (Audio—D31:F5)
SID—Subsystem ID Register (Audio—D31:F5)
Address Offset:
Default Value:
Lockable:
The SID register, in combination with the Subsystem Vendor ID register make it possible for the
operating environment to distinguish one audio subsystem from the other(s). This register is
implemented as write-once register. Once a value is written to it, the value can be read back. Any
subsequent writes will have no effect. This register is not affected by the D3
Address Offset:
Default Value:
Lockable:
This register indicates the offset for the capability pointer.
INTR_LN—Interrupt Line Register (Audio—D31:F5)
Address Offset:
Default Value:
Lockable:
This register indicates which PCI interrupt line is used for the AC ’97 module interrupt.
15:0
Bit
7:0
Bit
7:0
Bit
Capabilities Pointer (CAP_PTR) — RO. This field indicates that the first capability pointer offset is
offset 50h
Interrupt Line (INT_LN) — R/W. This data is not used by the ICH4. It is used to communicate to
software the interrupt line that the interrupt pin is connected to.
Subsystem ID — R/Write-Once.
2E
0000h
No
34h
50h
No
3Ch
00h
No
–
2Fh
Description
Description
Description
AC ’97 Audio Controller Registers (D31:F5)
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
R/WO
16 bits
Core
RO
8 bits
Core
R/W
8 bits
Core
HOT
to D0 transition.
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